Computer Architecture I: Digital Design Dr. Robert D. Kent

1. Computer Architecture I: Digital Design Dr. Robert D. Kent Logic Design Medium Scale Integration and Programmable Logic Devices Part I

2. Review • We have studied and developed several techniques for simplifying Boolean expressions. • These are based on the axioms, definitions and theorems of the Boolean Algebra, applied through the Boolean Calculus. • Powerful tabular techniques have been developed for rapid reduction to some minimal cost forms (ie. Karnaugh maps) • Now it is time to apply our knowledge and understanding to practical problems, eventually leading us to an understanding of the design issues and approaches in modern computer and network engineering.

3. Goals • At the outset of designing a complex system, such as a modern computer or network, it is clear that design is extraordinarily difficult and computationally challenging when performed at the level of fundamental Boolean logic gates. • For these reasons modern design approaches are based on hierarchical, component based methods. • Leading to simplified, localized component design, • lowering of design costs, • shifting some aspects of design to the component interface (the compatibility problem). • We will now begin to study logic design in the contexts of Medium Scale Integration (MSI) of gate devices and programmable logic devices (PLD).

4. Goals • We begin our study with simple, but functional circuits • we will construct a small library of useful components • we will seek to identify these components for their re-use potential

5. Goals • We begin our study with simple, but functional circuits • we will construct a small library of useful components • we will seek to identify these components for their re-use potential • At this stage we will have shifted our understanding from a model based on small-scale integrated circuits (SSI) to a different model based on medium-scale integrated circuits (MSI)

6. Goals • We begin our study with simple, but functional circuits • we will construct a small library of useful components • we will seek to identify these components for their re-use potential • At this stage we will have shifted our understanding from a model based on small-scale integrated circuits (SSI) to a different model based on medium-scale integrated circuits (MSI) • We must consider two distinct types of MSI circuits • Combinational circuits • Sequential circuits • We continue now with a study of Combinational circuits.

7. Circuit # 1 : Half-Adder

8. Circuit # 1 : Half-Adder • We begin by designing a circuit that will perform numeric (integer) addition of two input values.

9. Circuit # 1 : Half-Adder • We begin by designing a circuit that will perform numeric (integer) addition of two input values. • Assume that A and B each represent a single data bit, with possible numeric values 0 and 1.

10. Circuit # 1 : Half-Adder C A+ B S • We begin by designing a circuit that will perform numeric (integer) addition of two input values. • Assume that A and B each represent a single data bit, with possible numeric values 0 and 1. • The problem is to design a circuit that is able to model the addition operation: • Assume two inputs, A and B,

11. Circuit # 1 : Half-Adder C A+ B S • We begin by designing a circuit that will perform numeric (integer) addition of two input values. • Assume that A and B each represent a single data bit, with possible numeric values 0 and 1. • The problem is to design a circuit that is able to model the addition operation: • Assume two inputs, A and B, • Output: • a sum bit, S,

12. Circuit # 1 : Half-Adder • We begin by designing a circuit that will perform numeric (integer) addition of two input values. • Assume that A and B each represent a single data bit, with possible numeric values 0 and 1. • The problem is to design a circuit that is able to model the addition operation: • Assume two inputs, A and B, • Output: • a sum bit, S, • and, a carry bit, C. C A+ B S

13. Circuit # 1 : Half-Adder A B SC HA • We begin by designing a circuit that will perform numeric (integer) addition of two input values. • Assume that A and B each represent a single data bit, with possible numeric values 0 and 1. • The problem is to design a circuit that is able to model the addition operation: • Assume two inputs, A and B, • Output: • a sum bit, S, • and, a carry bit, C. C A+ B S

14. Circuit # 1 : Half-Adder • We begin the design by constructing a 2-input/2-output truth tableA B S C0 0 0 0 0 + 0 = 0 (no carry)

15. Circuit # 1 : Half-Adder • We begin the design by constructing a 2-input/2-output truth tableA B S C0 0 0 0 0 1 1 0 0 + 1 = 1 (no carry)

16. Circuit # 1 : Half-Adder • We begin the design by constructing a 2-input/2-output truth tableA B S C0 0 0 0 0 1 1 01 0 1 0 1 + 0 = 1 (no carry)

17. Circuit # 1 : Half-Adder • We begin the design by constructing a 2-input/2-output truth tableA B S C0 0 0 0 0 1 1 01 0 1 0 1 1 0 1 1 + 1 = 0 (with a carry = 1)

18. Circuit # 1 : Half-Adder Use algebra for simple cases with only a few variables. • We begin the design by constructing a 2-input/2-output truth tableA B S C0 0 0 0 0 1 1 01 0 1 0 1 1 0 1 • We derive the following expressions for the S and C circuits:

19. Circuit # 1 : Half-Adder • We begin the design by constructing a 2-input/2-output truth tableA B S C0 0 0 0 0 1 1 01 0 1 0 1 1 0 1 • We derive the following expressions for the S and C circuits:S = A’B + AB’

20. Circuit # 1 : Half-Adder • We begin the design by constructing a 2-input/2-output truth tableA B S C0 0 0 0 0 1 1 01 0 1 0 1 1 0 1 • We derive the following expressions for the S and C circuits:S = A’B + AB’= A xor B

21. Circuit # 1 : Half-Adder • We begin the design by constructing a 2-input/2-output truth tableA B S C0 0 0 0 0 1 1 01 0 1 0 1 1 0 1 • We derive the following expressions for the S and C circuits:S = A’B + AB’ = A xor BC = AB

22. Circuit # 1 : Half-Adder • We begin the design by constructing a 2-input/2-output truth tableA B S C0 0 0 0 0 1 1 01 0 1 0 1 1 0 1 • We derive the following expressions for the S and C circuits:S = A’B + AB’ = A xor B C = AB • This circuit is called a Half-Adder.

23. Circuit # 1 : Half-Adder A B SC HA • Using the S and C circuit expressions for the Half-Adder circuit:S = A’B + AB’ = A xor B C = AB we can represent the circuit schematically in terms of gate logics.

24. Circuit # 1 : Half-Adder Half-AdderAND/OR logic HA A B SC A B SC HA • Using the S and C circuit expressions for the Half-Adder circuit:S = A’B + AB’ = A xor B C = AB we can represent the circuit schematically in terms of gate logics.

25. Circuit # 1 : Half-Adder Half-AdderAND/XOR logic Half-AdderAND/OR logic HA HA A B A B SC SC A B SC HA • Using the S and C circuit expressions for the Half-Adder circuit:S = A’B + AB’ = A r B C = AB we can represent the circuit schematically in terms of gate logics.

26. Circuit # 2 : Full-Adder

27. Circuit # 2 : Full-Adder • The problem is to design a circuit, called a Full-Adder, that is able to model the addition operation, assuming: • three inputs: A, B and Cin , • and two outputs: a sum bit, S, and a carry bit, Cout .

28. Circuit # 2 : Full-Adder • The problem is to design a circuit, called a Full-Adder, that is able to model the addition operation, assuming: • three inputs: A, B and Cin , • and two outputs: a sum bit, S, and a carry bit, Cout . • Assume that A, B and Cin each represent a single data bit, with possible numeric values 0 and 1. The input Cin corresponds to a carry bit generated from prior bit additions.

29. Circuit # 2 : Full-Adder • The problem is to design a circuit, called a Full-Adder, that is able to model the addition operation, assuming: • three inputs: A, B and Cin , • and two outputs: a sum bit, S, and a carry bit, Cout . • Assume that A, B and Cin each represent a single data bit, with possible numeric values 0 and 1. The input Cin corresponds to a carry bit generated from prior bit additions. • We will eventually generalize the variables • Inputs: AK , BKand CKOutputs: SKand CK+1

30. Circuit # 2 : Full-Adder • We begin the design by constructing a 3-input/2-output truth table:Cin A B S Cout

31. Circuit # 2 : Full-Adder • We begin the design by constructing a 3-input/2-output truth table:Cin A B S Cout0 0 0 0 0 0 0 1 1 00 1 0 1 00 1 1 0 1

32. Circuit # 2 : Full-Adder • We begin the design by constructing a 3-input/2-output truth table:Cin A B S Cout0 0 0 0 0 0 0 1 1 00 1 0 1 0 0 1 1 0 11 0 0 1 0 1 0 1 0 11 1 0 0 1 1 1 1 1 1

33. Circuit # 2 : Full-Adder • We begin the design by constructing a 3-input/2-output truth table:Cin A B S Cout0 0 0 0 0 0 0 1 1 00 1 0 1 0 0 1 1 0 11 0 0 1 0 1 0 1 0 11 1 0 0 1 1 1 1 1 1 • This leads to the expressions:S = Cin’A’B + Cin’AB’ + CinAB + CinA’B’

34. Circuit # 2 : Full-Adder • We begin the design by constructing a 3-input/2-output truth table:Cin A B S Cout0 0 0 0 0 0 0 1 1 00 1 0 1 0 0 1 1 0 11 0 0 1 0 1 0 1 0 11 1 0 0 11 1 1 1 1 • This leads to the expressions:S = Cin’A’B + Cin’AB’ + CinAB + CinA’B’Cout = CinAB + Cin’AB + CinA’B + CinAB’

35. Circuit # 2 : Full-Adder Cin A B S Cin FA • We begin the design by constructing a 3-input/2-output truth table:Cin A B S Cout0 0 0 0 0 0 0 1 1 00 1 0 1 0 0 1 1 0 11 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 • This leads to the expressions:S = Cin’A’B + Cin’AB’ + CinAB + CinA’B’ Cout = CinAB + Cin’AB + CinA’B + CinAB’

36. Circuit # 2 : Full-Adder • Proceeding from the expressions:S = Cin’A’B + Cin’AB’ + CinAB + CinA’B’ Cout = Cout = CinAB + Cin’AB + CinA’B + CinAB’ and recalling that x’y+xy’ = x xor y, we derive the alternative expressions:

37. Circuit # 2 : Full-Adder • Proceeding from the expressions:S = Cin’A’B + Cin’AB’ + CinAB + CinA’B’ Cout = AB + CinA’B + CinAB’and recalling that x’y+xy’ = x xor y, we derive the alternative expressions:S = Cin’ (A xor B) + Cin (A xor B)’

38. Circuit # 2 : Full-Adder • Proceeding from the expressions:S = Cin’A’B + Cin’AB’ + CinAB + CinA’B’ Cout = AB + CinA’B + CinAB’and recalling that x’y+xy’ = x r y, we derive the alternative expressions:S = Cin’ (A xor B) + Cin (A xor B)’ = CinxorA xor B

39. Circuit # 2 : Full-Adder • Proceeding from the expressions:S = Cin’A’B + Cin’AB’ + CinAB + CinA’B’ Cout = AB + CinA’B + CinAB’and recalling that x’y+xy’ = x r y, we derive the alternative expressions:S = Cin’ (A xor B) + Cin (A xor B)’ = CinxorA xor B Cout = CinAB + Cin’AB + CinA’B + CinAB’

40. Circuit # 2 : Full-Adder • Proceeding from the expressions:S = Cin’A’B + Cin’AB’ + CinAB + CinA’B’ Cout = AB + CinA’B + CinAB’and recalling that x’y+xy’ = x r y, we derive the alternative expressions:S = Cin’ (A xor B) + Cin (A xor B)’ = CinxorA xor B Cout = CinAB + Cin’AB + CinA’B + CinAB’ = (Cin + Cin’)AB + Cin(A+A’)B + CinA(B+B’)

41. Circuit # 2 : Full-Adder • Proceeding from the expressions:S = Cin’A’B + Cin’AB’ + CinAB + CinA’B’ Cout = AB + CinA’B + CinAB’and recalling that x’y+xy’ = x r y, we derive the alternative expressions:S = Cin’ (A xor B) + Cin (A xor B)’ = CinxorA xor B Cout = CinAB + Cin’AB + CinA’B + CinAB’ = (Cin + Cin’)AB + Cin(A+A’)B + CinA(B+B’) = AB + CinB + CinA

42. Circuit # 2 : Full-Adder Cin A B S Cout FA • The representation of the Full-Adder circuit using gate logics is:S = CinxorA xor B Cout = AB + CinB + CinA

43. Circuit # 2 : Full-Adder Binary Full Adder FA Cin AB Cin A B SCout S Cout FA • The representation of the Full-Adder circuit using gate logics is:S = CinxorA xor B Cout = AB + CinB + CinA

44. Circuit # 2 : Full-Adder Binary Full Adder FA CK AK BK CK AKBK SKCK+1 SK CK+1 FA • Adapting the notation to a general set of input and output bits:SK = CKxorAKxor BK CK = AKBK + CKBK + CKAK

45. Circuit # 3 : Multi-bit Adder

46. Circuit # 3 : Multi-bit Adder • We may now use the previous results to construct a circuit to perform addition of two multi-bit inputs, A and B.

47. Circuit # 3 : Multi-bit Adder • We may now use the previous results to construct a circuit to perform addition of two multi-bit inputs, A and B. • Inputs: A = {A3 , A2, A1, A0} and B = { B3, B2, B1, B0 }Restrict attention to the 4-bit case (easy to generalize to N-bits).

48. Circuit # 3 : Multi-bit Adder Cout C3 C2 C1 A3 A2 A1 A0 + B3 B2 B1 B0 S3 S2 S1 S0 • We may now use the previous results to construct a circuit to perform addition of two multi-bit inputs, A and B. • Inputs: A = {A3 , A2, A1, A0} and B = { B3, B2, B1, B0 }

49. Circuit # 3 : Multi-bit Adder Cout C3 C2 C1 A3 A2 A1 A0 + B3 B2 B1 B0 S3 S2 S1 S0 • We may now use the previous results to construct a circuit to perform addition of two multi-bit inputs, A and B. • Inputs: A = {A3 , A2, A1, A0} and B = { B3, B2, B1, B0 } • Outputs: S = { S3, S2, S1, S0 } and Cout.

50. Circuit # 3 : Multi-bit Adder Cout C3 C2C1 A3 A2 A1A0 + B3 B2 B1B0 S3 S2 S1S0 • We may now use the previous results to construct a circuit to perform addition of two multi-bit inputs, A and B. • Inputs: A = {A3 , A2, A1, A0} and B = { B3, B2, B1, B0 } • Outputs: S = { S3, S2, S1, S0 } and Cout.