Reiner Hartenstein University of Kaiserslautern

1. July 8, 2002, ENST, Paris, France Enabling Technologies for Reconfigurable Computing and Software / Configware Co-Design Part 3:Resources for RC- Reiner Hartenstein University of Kaiserslautern

2. Schedule 2

3. Opportunities by new patent laws ? • to clever guys being keen on patents: • don‘t file for patent following details ! • everything shown in this presentation has been published years ago 3

4. >> Configware Industry • Configware Industry • Terminology • MoPL data-procedural language • Anti architecture and circuitry • Stream-based Memory Architecture http://www.uni-kl.de 4

5. Configware heading for mainstream • Configware market taking off for mainstream • FPGA-based designs more complex, even SoC • No design productivity and quality without good configware libraries (soft IP cores) from various application areas. • Growing no. of independent configware houses (soft IP core vendors) and design services • AllianceCORE & Reference Design Alliance • Currently the top FPGA vendors are the key innovators and meet most configware demand. 5

6. OS for PLDs • separate EDA software market, comparable to the compiler / OS market in computers, • Cadence, Mentor, Synopsys just jumped in. • < 5% Xilinx / Altera income from EDA SW 6

7. The Software AllianceEDA Program ... Xilinx Inc.'s Foundation... free WebPACK downloadable tool palette The Xilinx XtremeDSP Initiative (with Mentor Graphics) MathWorks / Xilinx Alliance. The Wind River / Xilinx alliance Xilinx Alliances • # 7

8. provides a wide selection of EDA tools Acugen Software, Agilent EEsof EDA, Aldec, Aptix, Auspy Development, Cadence, Celoxica, Dolphin Integration, Elanix, Exemplar, Flynn Systems, Hyperlynx, The Software Alliance EDA Program IKOS Systems, Innoveda, Mentor Graphics, MiroTech, Model Technoloy, Protel International, Simucad, SynaptiCAD, Synopsys, Synplicity, Translogic, Virtual Computer Corporation. helps leading EDA vendors to integrate Xilinx Alliance software tightly into their tools 8

9. The Xilinx AllianceCORE program Amphion Semiconductor, Ltd. ARC Cores CAST, Inc. DELTATEC Derivation Systems, Inc. Dolphin Integration (Grenoble) Eureka Technology Inc. Frontier Design Inc. GV & Associates, Inc. inSilicon Corporation iCODING Technology Inc. Loarant Corporation Mindspeed Technologies - A Conexant Business (formerly Applied Telecom) | a cooperation between Xilinx and third-party core developers, to produce a broad selection of industry-standard solutions for use in Xilinx platforms. - Partners are: MemecCore Mentor Graphics Inventra NewLogic Technologies, Inc. (Europe) NMI Electronics Paxonet Communications, Inc. Perigee, LLC Rapid Prototypes Inc. sci-worx GmbH (Hannover, Germany) SysOnChip TILAB (Telecom Italia Lab) VAutomation Virtual IP Group, Inc. XYLON. 9

10. The Xilinx Reference Design Alliance Program The Xilinx Reference Design Alliance Program helps the development of multi-component reference designs that incorporate Xilinx devices and other semiconductors. The designs are fully functional, but no warranties, no liability. Partners are:. JK microsystems, Inc. LYR Technologies NetLogic Microsystems ADI Engineering Innovative Integration 10

11. The Xilinx University Program The Xilinx University Program provides • Xilinx Student Edition Software, • Professor Workshops, • a Xilinx University User Group, • Presentation Materials and Lab Files, • Course Examples, • Research, • Books, etc. 11

12. Altera offers over a hundred IP cores (1) Altera offers over a hundred IP cores like, for example: • modulator, • synchronizer, • DDR SDRAM controller, • Hadamar transform, • interrupt controller, • Real86 16 bit microprocessor, • floating point, • FIR filter, • discrete cosine, • ATM cell processor, • and many others. • controller, • UART, • microprocessor, • decoder, • bus control, • USB controller, • PCI bus interface, • viterbi controller, • fast Ethernet • MAC receiver or transmitter, 12

13. Altera offers over a hundred IP cores (2) Modelware Ncomm, Inc. NewLogic Technologies Northwest Logic Nova Engineering, Inc. Palmchip Corporation Paxonet Communications PLD Applications Sciworx Simple Silicon Tensilica TurboConcept. from Altera | AMIRIX Systems, Inc. Amphion Semiconductor, Ltd. Arasan Chip Systems, Inc. CAST, Inc. Digital Core Design Eureka Technology Inc. HammerCores Innocor Ktech Telecommunications, Inc. Lexra Computing Engines Mentor Graphics - Inventra 13

14. Altera IP core design services Altera IP core design services are available from: • Northwest Logic 14

15. Altera Certified Design Center (CDC) Program Certified Design Center (CDC) Program: • Barco Silex • El Camino GmbH • Excel Consultants • Plextek • Reflex Consulting • Sci-worx • Tality • Zaiq Technologies. 15

16. The Altera Consultants Alliance Program (ACAP): The Altera Consultants Alliance Program (ACAP): lists • 41 offices in North America and • 29 in the rest of the world. 16

17. Devlopment boards Devlopment boards are offered from: • Altera • El Camino GmbH • Gid'el Limited • Nova Engineering, Inc. • PLD Applications • Princeton Technology Group • RPA Electronics Design, LLC • Tensilica. 17

18. Consultants and services not listed by Xilinx nor Altera (index) Flexibilis, Tampere, Finland, Geoff Bostock Designs, Wiltshire, England, Great River Technology, Alberquerque, NM, New Horizons GB Ltd, United Kingdom, North West Logic Silicon System Solutions, Canterbury, Australia, Smartech, Tampere, Finland, Tekmosv, Austin, Texas, The Rockland Group, Garden Valley, CA Nick Tredennick, Los Gatos, California, Vitesse, Algotronix, Edinburgh, Andraka Consulting Group Arkham Technology, Pasadena, CA Barco Silex, Louvain-la-Neuve, Belgium, Bottom Line Technologies, Milford, NJ Codelogic, Helderberg, South Africa, Coelacanth Engineering, Norwell, MASS Comit Systems, Inc., Santa Clara, CA EDTNProgrammableLogicDesignCenter 18

19. Consultants and services not listed by Xilinx nor Altera (1) Algotronix, Edinburgh, Reconfigurable Computing and FPL in software radio, communications and computer security Andraka Consulting Group high performance FPGA designs for DSP applications Arkham Technology, Pasadena, low cost IP cores for Xilinx and Atmel, embedded processor, DSP, wireless communication, COM / CORBA / DirectX, client-server database programming, software internationalization, PCB design Barco Silex, Louvain-la-Neuve, Belgium, IP integration boards for ASIC and FPGA, consultancy, design, sub-contracting 19

20. Consultants and services not listed by Xilinx nor Altera (2) Bottom Line Technologies, Milford, New Jersey, FPGA design, training, designing Xilinx parts since 1985 Codelogic, Helderberg, South Africa, consulting, FPGA design services Coelacanth Engineering, Norwell, Massachusetts, design services, test development services, in wireless communication, DSP-based instrumentation, mixed-signal ATE Comit Systems, Inc., Santa Clara, California, DSP, ASIC, networking, embedded control in avionics -- FPGA / ASIC design and system software EDTN Programmable Logic Design Center 20

21. Consultants and services not listed by Xilinx nor Altera (3) FirstPass, Castle Rock, Colorado Vitesse, ASIC design Flexibilis, Tampere, Finland, VHDL IP cores for Xilinx products Geoff Bostock Designs, Wiltshire, England, FPGA design services Great River Technology, Alberquerque, New Mexico, FPGA design services in digital video and point-to-point data transmission for aerospace, military, and commercial broadcasters New Horizons GB Ltd, United Kingdom, FPGA design and training, Xilinx specialist North West Logic; FPGA and embedded processor design in digital communications, digital video 21

22. Consultants and services not listed by Xilinx nor Altera (4) Silicon System Solutions, Canterbury, Australia, VHDL IP cores for the ASIC and FPGA/CPLD/EPLD markets Smartech, Tampere, Finland, ASIC and FPGA design Tekmosv, Austin, Texas, Multiple Designs on a Single Gate Array, HDL synthesis, design conversions, chip debug, test generation The Rockland Group, Garden Valley, California, a TeleConsulting organization about logic design for FPGAs Nick Tredennick, Los Gatos, California, investor and consultant 22

23. >> Terminology • Configware Industry • Terminology • MoPL data-procedural language • Anti architecture and circuitry • Stream-based Memory Architecture http://www.uni-kl.de 23

24. Terminology 24

25. Terminology & Acronyms • RC: reconfigurable computing • RL: reconfigurable logic • Software (SW): procedural sources* • Configware (CW): structural sources • Hardware (HW): hardwired platforms • ASIC: customizable hardwired platforms • Flexware (FW): reconfigurable platforms • FPGA: field-programmable gate array • FPL: field-programmable logic *) note: firmware is SW ! 25

26. Stream-based Computing (2) terms: • DPU: datapath unit • DPA: datapath array • rDPU: reconfigurable DPU • rDPA: reconfigurable DPA • stream-based computing: using complex pipe network (super-systolic: Kress et al.) 26

27. Confusing Terminology Computer Science and EE as well as ist R&D and applicatgion areas suffer from a babylonial confusion. Communication not only between Computer Science and EE, but also between ist special areas, even between ist different abstrac tion levels is made difficult – mainly because of immature terminology in relation to reconfigurable circuits and their applications. Terms are rarely standardized and often used with drastically different meanings – even within then same special area. Often terms have been so badly coined, that they are not self-explanatory, but mesleading. A demonstratory example is the comparizon of terms used used in VHDL and Verilog.   Ideal are "intuitive" terms. But often Intuition yields the wrong idea. Whenever a new term appears in teaching, I often have to tell the students, that the term does not mean, what he believes.   27

28. . Terms (1) [à la Ingo Kreuz] 28

29. . Terms (2) [à la Ingo Kreuz] 29

30. . Terms (3) [à la Ingo Kreuz] 30

31. Hardware Terms (1) [à la Ingo Kreuz] *) processing datastreams (transport-triggered), not yet a machine: autosequencing memory missing 31

32. Hardware Terms (2) [à la Ingo Kreuz] 32

33. Terms on Parallelism (1) [à la Ingo Kreuz] 33

34. Terms on Parallelism (2) [à la Ingo Kreuz] 34

35. Terms on Parallelism (3) [à la Ingo Kreuz] 35

36. Counterparts [à la Ingo Kreuz] 36

37. >> MoPL data-procedural language • Configware Industry • Terminology • MoPL data-procedural language • Anti architecture and circuitry • Stream-based Memory Architecture http://www.uni-kl.de 37

38. Fundamental Ideas available (1) • Data Sequencer Methodology • Data-procedural Languages (Duality with v N) • ... supporting memory bandwidth optimization • Soft Data Path Synthesis Algorithms • Parallelizing Loop Transformation Methods • Compilers supporting Soft Machines • SW / CW Partitioning Co-Compilers 38

39. Fundamental Ideas available (2) • Programming Xputers • Similarities to programming computers • How not to get confused by similarities • What benefits vs. Computers ? 39

40. Programming Language Paradigms easy to learn 40

41. Similar Programming Language Paradigms very easy to learn 41

42. *> Declarations goto PixMap[1,1] HalfZigZag; SouthWestScan uturn (HalfZigZag) x EastScan is step by [1,0] end EastScan; 4 y SouthScan is step by [0,1] endSouthScan; 1 NorthEastScan is loop8 times until [*,1] step by [1,-1] endloop end NorthEastScan; HalfZigZag HalfZigZag 2 data counter data counter SouthWestScan is loop8 times until [1,*] step by [-1,1] endloop end SouthWestScan; 3 HalfZigZag is EastScan loop 3 times SouthWestScan SouthScan NorthEastScan EastScan endloop end HalfZigZag; data counter data counter JPEG zigzag scan pattern published in 1993 42

43. >> Anti architecture and circuitry • Configware Industry • Terminology • MoPL data-procedural language • Anti architecture and circuitry • Stream-based Memory Architecture http://www.uni-kl.de 43

44. D B A L 0 GAG = Generic Address [ ] | | | | Generatorc DA L0 B0 limit Address Stepper Base Slider Limit Slider all 3 are copies of the same BSU stepper circuit A GAU generic address unit Scheme published in 1990 GAU 44

45. GAG: Address Stepper ] [ Generic Basic Address Stepper Base stepVector maxStepCount Limit | | Unit Generator GAG = BSU = B 0 init tag Step D A L A Counter =o + / – sequencing D B A L 0 Escape [ ] | | | | End stepper Clause Detect limit A endExec Address GAG: Address Stepper published in 1990 45

46. DA L0 B0 Address Stepper Base Slider Limit Slider a) b) GAU A c) until d) e) f) g) Generic Sequence Examples atomic scan linear scan video scan -90º rotated video scan -45º rotated (mirx (v scan)) sheared video scan non-rectangular video scan zigzag video scan spiral scan feed-back-driven scans perfect shuffle published in 1990 46

47. floor B F 0 Slider Animation Demo published in 1990 address 47

48. GAU GAU DA DA DA L0 L0 L0 B0 B0 B0 VLIW stack GAG Address Stepper Address Stepper Address Stepper Base Slider Base Slider Base Slider Limit Slider Limit Slider Limit Slider GAU GAU GAU A A A SDS GAG GAG Complex Sequencer Implementation all `been published in 1990 Generic Address Generator 48

49. >> Stream-based Memory Architecture • Configware Industry • Terminology • MoPL data-procedural language • Anti architecture and circuitry • Stream-based Memory Architecture http://www.uni-kl.de 49

50. Smart memory interface rDPA Multiple RAM banks Scan Window „Cache“ MoM Xputer Architecture published in 1990 50