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On Chip Bus

On Chip Bus. Speaker: 沈文中. National Taiwan University Adopted from National Taiwan University SOC Course Material. Outline. AMBA Bus Advanced System Bus Advanced High-performance Bus Advanced Peripheral Bus IP Design flow FPGA design flow. Bus Architecture. Outline. AMBA Bus

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On Chip Bus

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  1. On Chip Bus Speaker: 沈文中 National Taiwan University Adopted from National Taiwan University SOC Course Material

  2. Outline • AMBA Bus • Advanced System Bus • Advanced High-performance Bus • Advanced Peripheral Bus • IP Design flow • FPGA design flow

  3. Bus Architecture

  4. Outline • AMBA Bus • Advanced System Bus • High performance • Pipelined operation • Multiple bus master • Advanced High-performance Bus • Advanced Peripheral Bus • IP Design flow • FPGA design flow

  5. ASB characters • Negative edge trigger • Tri-state bus • Drawback: More effort used to control timing • Advantage: cost less area

  6. Outline • AMBA Bus • Advanced System Bus • Advanced High-performance Bus • High performance • Pipelined operation • Multiple bus master • Burst transfers • Split transactions • Advanced Peripheral Bus • IP Design flow • FPGA design flow

  7. AHB simple Arch.

  8. AHB Components • AHB Components • AHB master is able to initiate read and write operations by providing an address and control information. Only one bus master is allowed to actively use the bus at any one time.(max. 16) • AHB slave responds to a read or write operation within a given address-space range. The bus slave signals back to the active master the success, failure or waiting of the data transfer.

  9. AHB Components(ii) • AHB Components • AHB arbiter ensures that only one bus master at a time is allowed to initiate data transfers. • AHB decoder is used to decode the address of each transfer and provide a select signal for the slave that is involved in the transfer. A single centralized decoder is required in all AHB implementations.

  10. AHB Signals(i) • AHB Signals can be classified as • Clock (HCLK) • Address and read/write data (HADDR, HRDATA, HWDATA) • Arbitration (HGRANTx, HMASTER, HMASTLOCK,…) • Control signal (HRESETn,…) • Response signal(HREADY, HRESP)

  11. AHB Signals(ii) • Transfer signals • HCLK • bus clock. All signal timings are related to the rising edge. • HADDR[31:0] • 32 bits system bus • HWDATA/HRDATA [31:0] • 32 bits write/read data bus • HWRITE • High: write data • Low: read data • HREADY • Transfer done

  12. AHB Signals(ii)Basic Transfer • Each transfer consists of • An address and control cycle • One or more cycles for the data

  13. AHB Arch.

  14. AHB Signals(iii) • Control signals • HTRANS[1:0] • Current transfer type • HBURST[2:0] • When sequential transfer, control transfer relation • HSIZE[2:0] • Control transfer size=2^HSIZE bytes(max=1024bits) • HPROT[3:0] • Protection data

  15. AHB Signals(iii)-HTRANS • HTRANS[1:0] • IDLE: master don’t need data to be transfered • BUSY: allows bus masters to insert IDLE cycles in the middle of bursts of transfers. • NONSEQ: The address and control signals are unrelated to the previous transfer. • SEQ: the address is related to the previous transfer.

  16. AHB Signals(iii)-HBURST

  17. AHB Signals(iii)-HBURST

  18. AHB Signals(iv) • Response signals • HREADY • Transfer done, ready for next transfer • HRESP[1:0] • OKAY transfer complete • ERROR transfer failure(ex: write ROM) • RETRY higher priority master can access bus • SPLIT other master can access bus

  19. AHB Signals(v) • Arbiter signals • HGRANTx • Select active bus master • HMASTER[3:0] • Multiplex signals that sent from master to slave • HMASTLOCK • Locked sequence

  20. Master signal

  21. Arbiter signal

  22. Slave signal

  23. Outline • AMBA Bus • Advanced System Bus • Advanced High-performance Bus • Advanced Peripheral Bus • Low power • Latched address and control • Simple interface • Suitable for many peripherals • IP Design flow • FPGA design flow

  24. APB state diagram

  25. APB signals • APB character • Always two cycle transfer • No wait cycle and response signal • APB signals • PCLK Bus clock，rising edge is used to time all transfers. • PRESETn APB reset。active Low.

  26. APB signals • PADDR[31:0] APB address bus. • PSELx Indicates that the slave device is selected. There is a PSELx signal for each slave. • PENABLE Indicates the second cycle of an APB transfer. • PWRITE Transfer direction. High for write access, Low for read access. • PRDATA Read data bus • PWDATA Write data bus

  27. Outline • AMBA Bus • Advanced System Bus • Advanced High-performance Bus • Advanced Peripheral Bus • IP Design flow • Memory definition • IP design-SW • IP design-HW • FPGA design flow

  28. Memory definition • Self-designed IP can be located in the Bus error response area • Defined in AHBDecoder.v

  29. Slave #2 Logic Module Slave #1 APB AHB Slave #3 MYIP AMBA IP design (1/4) • Add an IP (MYIP) into the system which includes • a ZBT SSRAM controller • an AHB to APB bridge • an APB register peripheral • an APB interrupt controller • an address decoder

  30. Slave #2 Slave #3 Slave #1 AMBA IP design (2/4) • Supplied HDL file • AHBAHBTop.v • AHBDecoder.v • AHBMuxS2M.v • AHBZBTRAM.v • AHB2APB.v • AHBAPBSys.v • APBIntCon.v • APBRegs.v

  31. Arbiter Decoder Slave #1 Master #1 HSEL HADDR HADDR HWDATA HADDR HWDATA HRDATA Mux HRDATA HWDATA Slave #2 Mux HSEL HADDR Master #2 HWDATA HADDR HRDATA HWDATA HRDATA Mux HRDATA Slave #3 HSEL HADDR HWDATA HRDATA Logic Module AMBA IP design (3/4) • Bus Interconnection

  32. AMBA IP design (4/4) • Software part • Write a function to control hardware • Delay number of clocks by NOOP (asm) instruction • Hardware part • Design your own IP module MYIP.v • Change AHBDecoder.v • Change AHBMuxS2M.v • Change AHBAHBTop.v to include MYIP into top module

  33. MYIP.v HCKL AHB Slave Interface HRESETn HSEL HREADYIn HTRANS MYIP circuit HSIZE HWRITE IDLE HADDR HWDATA HREADYOut WRITE READ HRESP HRDATA IP design-HW (1/4) • Design your own IP module MYIP.v • Write your own module MYIP.v with AMBA AHB Slave interface

  34. HSEL_S1 HSEL_S2 Decoder HSELMYIP Slave #1 Master #1 HSEL HADDR HADDR_M1[31:0] HADDR HWDATA HWDATA HADDR to all slaves HRDATA Mux HRDATA Address and control mux Slave #2 HSEL HADDR Master #2 HWDATA HADDR HRDATA HADDR_M2[31:0] HWDATA HRDATA MYIP HSEL HADDR HWDATA HRDATA Logic Module IP design-HW (2/4) • Change AHBDecoder.v • Add HSELMYIP signal to select MYIP to response • Address are defined in decoder

  35. Slave #1 Decoder HSEL HADDR HWDATA HRDATA Slave #2 HSEL HADDR Master HWDATA HADDR HRDATA HWDATA HRDATA Mux HRDATA MYIP HSEL HADDR HWDATA HRDATA Logic Module IP design-HW (3/4) • Change AHBMuxS2M.v • Use Mux to select slave which can use HRDATA

  36. Decoder Slave #1 HSEL HADDR HADDR HWDATA HRDATA HWDATA Slave #2 HSEL HADDR HWDATA HRDATA HRDATA Mux MYIP HSEL HADDR HWDATA HRDATA Logic Module IP design-HW (4/4) • Change AHBAHBTop.v • Add your module in AMBA bus • Connect the above net connection

  37. AHBAHBTop addr sel AHBDecoder AHBMuxS2M MYIP AHBZBTRAM AHBAPBsys ZBTSRAM AHB2APB APBIntCon APBregs Architecture

  38. Files Description of Example • Hardware files .\Lab6\Codes\HW\Verilog\ • AHBAHBTop.v • AHBDecoder.v • AHBMuxS2M.v • AHBZBTRAM.v • AHB2APB.v • AHBAPBSys.v • APBIntCon.v • APBRegs.v • MYIP.v • Software program files .\Lab6\Codes\SW\ • sw.mcp • register.c • platform.h • rw_support.s For FPGA synthesis tool to generate bitstream For CodeWarrior to generate sw.axf

  39. HCKL AHB Slave Interface HRESETn HSEL HREADYIn HTRANS MYIP circuit HSIZE HWRITE HADDR IDLE HWDATA HREADYOut HRESP READ WRITE HRDATA Hardware file MYIP.v • MYIP.v • A simple IP template with 8 32-bit registers wrapped with simple AHB slave interface • This file is modified from AHBZBTRAM.v

  40. Outline • AMBA Bus • Advanced System Bus • Advanced High-performance Bus • Advanced Peripheral Bus • IP Design flow • FPGA design flow • Compile flow & Download flow (Xilinx) • Compile flow & Download flow (Altera)

  41. Compile flow (1/2) (Xilinx) • All Verilog module must be synthesized by Xilinx Software

  42. Compile flow (2/2) (Xilinx) • Add register.ucf (define the pin assignment) into project • Double click generate programming file to generate *.bit (which can be downloaded into FPGA)

  43. Download flow (Xilinx) • Connect config link • Connect Multi-ICE to Logic Module • Power on • Use progcards.exe to download register.bit file • Remove config link • Power off

  44. Outline • AMBA Bus • Advanced System Bus • Advanced High-performance Bus • Advanced Peripheral Bus • IP Design flow • FPGA design flow • Compile flow & Download flow (Xilinx) • Compile flow & Download flow (Altera)

  45. Compile flow (1/2) (Altera) • All Verilog module must be synthesized by Altera Software (Quartus II)

  46. Compile flow (2/2) (Altera) • Modify Pinout.csf into ahbahbtop.csf to define the pin assignment • Push the Compile bottom to generate *.rbf (which can be downloaded into FPGA)

  47. Download flow (Altera) • Use the text-editor to produce a .brd file (configuration file for progcards.exe) • Power off • Connect Multi-ICE to Logic Module • Set the LM in Config Mode • Power on • Auto-config again in the MultiICE Server program • Use progcards.exe to download bitstream

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