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A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures

A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures. Author: J. Kim, C. Nicopoulos (Dept. of CSE, PSU) Speaker: Po-Shan Huang ISCA’07. Outline. Introduction Current 3D NoC Architecture Proposed DimDe Router Experimental Results Conclusion. Outline.

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A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures

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  1. A Novel Dimensionally-Decomposed Router for On-ChipCommunication in 3D Architectures Author: J. Kim, C. Nicopoulos (Dept. of CSE, PSU) Speaker: Po-Shan Huang ISCA’07

  2. Outline • Introduction • Current 3D NoC Architecture • Proposed DimDe Router • Experimental Results • Conclusion

  3. Outline • Introduction • Current 3D NoC Architecture • Proposed DimDe Router • Experimental Results • Conclusion

  4. Introduction • a new 3D NoC router architecture • Partially-connected Dimensionally-Decomposed (DimDe) Router • Characteristics • True 3D crossbar structure • Varying the number of vertical connections • Segmented vertical links in the partially-connected crossbar • Hierarchical arbitration scheme for inter-strata transfers • Similar to the Row-Column (RoCo) Decoupled Router

  5. Face-to-Back bonding

  6. Outline • Introduction • Current 3D NoC Architecture • Proposed DimDe Router • Experimental Results • Conclusion

  7. Area and Power Comparisons of the Crossbar Switches

  8. 3D Symmetric NoC Architecture • 7x7 crossbar

  9. 3D NoC-Bus Hybrid Architecture • 6x6 crossbar

  10. A True 3D NoC Router

  11. A True 3D NoC Router (cont.)

  12. Outline • Introduction • Current 3D NoC Architecture • Proposed DimDe Router • Experimental Results • Conclusion

  13. 3D DimDe NoC Architecture

  14. 3D DimDe NoC Architecture

  15. 3D DimDe NoC Architecture

  16. Outline • Introduction • Current 3D NoC Architecture • Proposed DimDe Router • Experimental Results • Conclusion

  17. Simulation Platform • Server workloads • TPC-C • SAP • Memory traces • SPLASH • Simulator • Simics • The baseline configuration • Solaris 9 Operating system • eight UltraSPARC III cores

  18. Simulation Platform (cont.) • Energy Model • Register-Transfer Level (RTL) Verilog • Synopsys Design Compiler • TSMC 90 nm standard cell library

  19. Impact of the Number of Vertical Bundles on Performance • Two vertical links instead of more

  20. Simulation Result • Latency and throughput improvements of over the other 3D architectures Latency Throughput

  21. Conclusion • Energy reduction within Slight performance overhead • Small crossbar and simple design reduce about 26% in terms of EDP • Within 5% overhead

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