Architecture and algorithm for synthesizable embedded programmable logic core

1. Architecture and algorithm for synthesizable embedded programmable logic core Noha Kafafi, Kimberly Bozman, Steven J. E. Wilton 2003 Field programmable gate arrays

2. Outline • Introduction • Two soft PLC architecture • CAD algorithm to program PLC • Experimental result • Non-rectangular fabric • Summary

3. Introduction • In order to make post-fabrication changes: programmable logic core (PLC) in SoC design • Shortcomings of PLC (“hard PLC”) • tools • must address physical connection & placement issue • PLC size • How about the “soft” PLC ?

4. Soft programmable logic core • A description of PLC’s behavior which is written in VHDL or verilog • Existing tools can be used to implement the chip • Can be positioned close to where it want • Can support needs precisely • Overhead of area, power, and speed is large! -> amount of PLC must be small !!

5. Partition the circuit Obtain the HDL of PLC Merge HDL of PLC and fixed part of circuit Use standard synthesis tools to generate IC Fabricate IC Program PLC Flow

6. Outline • Introduction • Two soft PLC architecture • directional architecture • gradual architecture • CAD algorithm to program PLC • Experimental result • Non-rectangular fabric • Summary

7. Directional Architecture • Straightforward way is to describe the behavior of a standard FPGA at RTL level using HDL • But there are some observations : • soft PLC only make sense for small amounts of programmable logic • many tools have problems with combinational loops

8. Directional Architecture • Implement combinational logic only • Limit the direction of flow

9. More efficient architecture • Small circuit -> can remove some flexibility • Since the core will be hardwired with other parts of the chip, we need lots of flexibility at the inputs and outputs • Each “tile” need not be same

10. Gradual Architecture

11. Outline • Introduction • Two soft PLC architecture • CAD algorithm to program PLC • Experimental result • Non-rectangular fabric • Summary

12. CAD algorithm to program PLC • Placement algorithms • simulated annealing • directional architecture : • avoid putting the source block at the right side of sink block • cost function depends on Manhattan distance • gradual architecture : • poor placement can easily lead to unroutable implementations • to minimized the overuse of routing multiplexers

13. Placement for gradual architecture

14. Placement for gradual architecture

15. CAD algorithm to program PLC • Routing algorithms • Turns out this is an easy problem • Normal FPGA routers work well

16. Outline • Introduction • Two soft PLC architecture • CAD algorithm to program PLC • Experimental result • Non-rectangular fabric • Summary

17. Experimental result Gradual is 18.9% less than directional

18. Experimental result • Soft and hard programmable logic cores • estimate the size of hard core by transistor-count model • focus on a 4 x 4 gradual architecture with three input multiplexers per row  hard PLC size is 12868μm2  soft PLC size is 81092μm2 so soft PLC is 6.4x less dense than the hard PLC! • comparison of speed and power are not finish….

19. Outline • Introduction • Two soft PLC architecture • CAD algorithm to program PLC • Experimental result • Non-rectangular fabric • Summary

20. Non-rectangular fabric • Logic circuit often have a triangular shape • Develop a more efficient architecture • If remove m blocks from column i, then remove m-1 blocks from column i-1 • Factor “c” : proportion of the logic blocks in the top row that have been removed

21. Non-rectangular fabric 11.1% lower than square core

22. Outline • Introduction • Two soft PLC architecture • CAD algorithm to program PLC • Experimental result • Non-rectangular fabric • Summary

23. Summary • Two soft PLC architecture • Soft PLC is 6.4x less efficient than hard PLC • Non-rectangular fabric