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Lecture 7

Lecture 7. Combinational Logic. Combinational Logic. Logic circuit for digital systems may be : combinational circuit. sequential circuit . A combinational circuit : consists of logic gates whose output at any time are determined from only present input.

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Lecture 7

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  1. Lecture 7 Combinational Logic Lecturer : May Aldoayan

  2. Combinational Logic • Logic circuit for digital systems may be : • combinational circuit. • sequential circuit . A combinational circuit : • consists of logic gates whose output at any time are determined from only present input. • Performs an operation that can be specified logically by set of Boolean functions. • No memory , no feedback path A Sequential circuit : • Output of sequential circuit depend not only on present values of input but also an past input . Lecturer : May Aldoayan

  3. Combinational Logic • A combinational circuits consists of input variable , logic gates and output variable . Lecturer : May Aldoayan

  4. Analysis Procedure • The diagram of a combinational circuit has logic gates with no feedback paths. • A feedback path is a connection from the output of one gate to the input of a second gate whose output forms part of the input to the first gate. Lecturer : May Aldoayan

  5. Analysis Procedure • To obtain the output Boolean functions from a logic diagram, we proceed as follows: • Label all gate outputs that are a function of input variables with arbitrary symbols but with meaningful names. Determine the Boolean functions for each gate output. • Label the gates that are a function of input variables and previously labeled gates with other arbitrary symbols. Find the Boolean functions for these gates. • Repeat the process outlined in step 2 until the outputs of the circuit are obtained. • By repeated substitution of previously defined functions, obtain the output Boolean functions in terms of input variables. Lecturer : May Aldoayan

  6. Analysis combinational circuits FIGURE 4.2 Logic diagram for analysis example Lecturer : May Aldoayan

  7. Analysis combinational circuits The analysis of the combinational circuit of Fig. 4.2 illustrates the proposed procedure. F2 = AB + AC + BC T1 = A + B + C T2 = ABC Next, we consider outputs of gates that are a function of already defined symbols: T3= F2’ T1 F1= T3 + T2 Lecturer : May Aldoayan

  8. Analysis combinational circuits F1 = T3 + T2 = F2’T1 + ABC = (AB + AC + BC )’ (A + B + C) + ABC = (A’ + B’) ( A’ + C’) ( B’ + C’) ( A + B + C ) + ABC =(A’ + B’C’) ( AB’ + AC’ + BC’ + B’C) + ABC = A’BC’ + A’B’C + AB’C’ + ABC Lecturer : May Aldoayan

  9. Table 4.1 Truth Table for the Logic Diagram of Fig. 4.2 Lecturer : May Aldoayan

  10. Analysis combinational circuits • To obtain the truth table directly from the logic diagram without going through the derivations of the Boolean functions, we proceed as follows: • Determine the number of input variables in the circuit. For n inputs, form the 2n possible input combinations and list the binary numbers from 0 to (2n – 1) in a table. • Label the outputs of selected with arbitrary symbols • Obtain the truth table for the outputs of those gates which are a function of the input variables only • Proceed to obtain the truth table for the outputs of theose gates which are a function of previously defined values until the columns for all outputs are determined. Lecturer : May Aldoayan

  11. DESIGN PROCEDURE • The design procedure involves the following steps : • from the specifications of the circuit , determine the required number of inputs and outputs and assign a symbol to each . • derive the truth table that defines the required relationship between inputs and outputs. • Obtain the simplified Boolean function for each output as a function of input variables . • Draw the logic diagram and verify the correctness of the design . Lecturer : May Aldoayan

  12. DESIGN PROCEDURE • Example 1 :Design a combinational circuit with 3 input X,Y,Z and 3 output A, B , C when the binary input is 0 , 1, 2 , 3 the binary output is 1 greater than the input , when the binary input is 4 , 5, 6, 7 the binary is 1 less than the input . Design steps : • determine input and output 3 input : X,Y , Z and 3 output : A , B , C Lecturer : May Aldoayan

  13. DESIGN PROCEDURE Design steps : 2. truth table : Lecturer : May Aldoayan

  14. DESIGN PROCEDURE Design steps : 3. Simplify: Lecturer : May Aldoayan

  15. DESIGN PROCEDURE Design steps : • 4. Diagram : Lecturer : May Aldoayan

  16. Code conversion Example : • To convert from binary code A to binary code B, the input lines must supply the bit combination of elements as specified by code A and the output lines must generate the corresponding bit combination of code B. • The design procedure will be illustrated by an example that converts binary coded decimal (BCD) and excess -3 codes for the decimal digits. Lecturer : May Aldoayan

  17. Code conversion Example : Table 4.2 Truth Table for Code Conversion Example Lecturer : May Aldoayan

  18. Code conversion Example : FIGURE 4.3 Maps for BCD-to-excess-3 code converter Lecturer : May Aldoayan

  19. Code conversion Example : FIGURE 4.4 Logic diagram for BCD-to-excess-3 code converter Lecturer : May Aldoayan

  20. BINARY ADDER-SUBTRACTOR • The combinational circuit the addition of two bits is called a half adder. • One thatperform the addition of three bits (two significant bits and a previous carry ) is a full adder. Half adder • This simple addition consists of four posibile elementary operations 0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1+ 1 = 10 • We assign symbols x and y to the two input variables • two output variables: C (carry), S (sum) • The truth table Lecturer : May Aldoayan

  21. BINARY ADDER-SUBTRACTOR Table 4.3 Half Adder Lecturer : May Aldoayan

  22. HALF ADDER FIGURE 4.5 Implementation of half adder Lecturer : May Aldoayan

  23. Example :design combinational circuit that perform the addition of two bits (half adder ) • The rule for the addition of two single bit number are defined Design steps : from the specifications of half adder , we find that this circuit needs two binary inputs and two binary output , we assign symbols x and y for input and s(sum) and c (carry) to the output . derive the truth table that defines the required relationship between inputs and outputs. Lecturer : May Aldoayan

  24. Design steps : 3. Obtain the simplified Boolean function for each output as a function of input variables . Function for output s Function for output c 1 1 1 S = x’ y + x y’ S = X + y c=xy Lecturer : May Aldoayan

  25. HALF ADDER S = x’ y + x y’ s =x + y Lecturer : May Aldoayan

  26. HALF ADDER • Block for half adder (HA) HA x s y c Lecturer : May Aldoayan

  27. FULL ADDER • Addition of n-bit binary numbers requires the use of a full adder, and the process of addition proceeds on a bit-by-bit basis, right to left, beginning with the least significant bit. • A full Adder is a combinational circuit that forms the arithmatic sum of three bits. • It consists of three inputs and two outputs. • Two of the inputs variables, denoted by x and y, represent the two significant bits to be added. • The third input z represent the carry from the previous lower significant position. • Two outputs are necessary because the arithmetic sum of three binary digits ranges in value from 0 and 3, and binary representation of 2 or 3 Lecturer : May Aldoayan

  28. FULL ADDER A full adder is similar to a half adder, but includes a carry-in bit from lower stages. Like the half-adder, it computes a sum bit, S and a carry bit, C. For a carry-in (Z) of 0, it is the same as the half-adder: For a carry- in (Z) of 1 Table 4.4 Full Adder Lecturer : May Aldoayan

  29. FULL ADDER 2. Obtain the simplified Boolean function for each output as a function of input variables . FIGURE 4.6 K-Maps for full adder Lecturer : May Aldoayan

  30. FIGURE 4.7 Implementation of full adder in sum-of-products form Lecturer : May Aldoayan

  31. Binary Adder • A binary adder is a digital circuit that procedures the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of the next full adder in the chain. • To demonstrate with a specific example, consider the two binary number A= 1011 and B = 0011. Their sum s = 110 is formed with the four-bit adder as follows: Lecturer : May Aldoayan

  32. Binary Adder FIGURE 4.9 Four-bit adder Lecturer : May Aldoayan

  33. DECODER • Discrete quantities of information are represented in digital systems by binary codes. • A binary code of n bits is capable of representing up to 2 n distinct elements of coded information. • The decoders are presented here are called n-to-m line decoder where m<= 2 n • The name decoder is also used in conjunction with other code converters, such as a BCD-to-seven-segment decoder. • As an example, consider the three – to- eight- line decoder circuit of Fig4.18 Lecturer : May Aldoayan

  34. All row of input create numberIf the created number = 0 then D0 = 1 another = 0 If the created number= 2 then D2 = 1 and another = 0 and so on Table 4.6 Truth Table of a Three-to-Eight-Line Decoder There are seven outputs that are equal to 0 and only one that is equal to 1. The output whose value is equal to 1 represent the minterm equivalent of the binary currently available in the input lines. Lecturer : May Aldoayan

  35. FIGURE 4.18 Three-to-eight-line decoder Lecturer : May Aldoayan

  36. DECODER • Design Decoder 2*4 ? • 1- determine input / output : • decoder 2* 4 has 2 input ( A , B ) and 22 = 4 output (D0 , D1 , D2 , D3 ) • 2- Truth Table : All row of input create number If the created number = 0 then D0 = 1 and onther = 0 If the created number= 2 then D2 = 1 and anthor = 0 and so Lecturer : May Aldoayan

  37. DECODER Lecturer : May Aldoayan

  38. DECODER with ENABLE • Some decoders are constructed with NAND gates. • Since a NAND gate produces the AND operation with an inverted output, it becomes more economical to generate the decoder minterms in their complemented form. • Decoders include one or more enable inputs to control the circuit operation. • A two – to – Four-line decoder with an enable input constructed with NAND gate shown in FIG 4.19. • The circuit operates with complemented outputs and a complement enable input. • The decoder is enabled when E is equal to 0 • The circuit is disabled when E is equal to 1 Lecturer : May Aldoayan

  39. DECODER with ENABLE FIGURE 4.19 Two-to-four-line decoder with enable input Lecturer : May Aldoayan

  40. DECODER Block of decoder 2* 4 Block of decoder 4* 16 Block of decoder 3* 8 Lecturer : May Aldoayan

  41. Design A decoder 3*8 using a decoder 2*4 with Enable and additional gate Lecturer : May Aldoayan

  42. Design A decoder 4*16 using a decoder 3*8 with Enable and additional gate FIGURE 4.20 4 × 16 decoder constructed with two 3 × 8 decoders Lecturer : May Aldoayan

  43. Combinational Logic implementation each output = a minterm use a decoder and an external OR gate to implement any Boolean function of n input variables S(x, y, z) = C (x ,y ,z) = FIGURE 4.21 Implementation of a full adder with a decoder Lecturer : May Aldoayan

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