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CSE 670 Embedded System Design Using FPGAs

CSE 670 Embedded System Design Using FPGAs. Prof. Richard E. Haskell 115 Dodge Hall. CSE 670 – Winter 2004. Prerequisites : Undergraduate course in digital design Programming in a high-level language. CSE 670 – Winter 2004. Text : None required References:

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CSE 670 Embedded System Design Using FPGAs

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  1. CSE 670Embedded System Design Using FPGAs Prof. Richard E. Haskell 115 Dodge Hall

  2. CSE 670 – Winter 2004 • Prerequisites: • Undergraduate course in digital design • Programming in a high-level language

  3. CSE 670 – Winter 2004 • Text: None required • References: • HDL Chip Design,Douglas J. Smith, Doone Publications, 1996. • Logic and Computer Design Fundamentals, 3rd Ed., by M. Morris Mano and Charles R. Kime, Prentice Hall, 2004. • The Student's Guide to VHDL, by Peter J. Ashenden, Morgan Kaufmann Publishers, Inc., San Francisco, 1998. • The Verilog Hardware Description Language, 3rd Ed., by Donald E. Thomas and Philip R. Moorby, Kluwer Academic Publishers, Boston, 1996.

  4. Course Contents • 1. CPLDs and FPGAs • 2. VHDL and Verilog • 3. Simulation and Synthesis of VHDL and Verilog models • 4. Modeling Combinational Logic Circuits • 5. Modeling Sequential Logic Circuits • 6. State Machines and Processors

  5. Course ObjectivesBy the end of the course you should be able to • Model any combinational circuit using VHDL. • Simulate VHDL designs using Active HDL. • Synthsize VHDL designs to Xilinx FPGAs. • Model registers and datapaths using VHDL. • Implement control logic using a finite state machine in VHDL. • Design a processor and implement it on a Xilinx FPGA. • Complete an FPGA design project and present and demonstrate the results.

  6. Labs • Lab for this course is in Room 133, SEB. • Get account at • http://cto.secs.oakland.edu • Lab available during class and at other times. • First lab done individually. • Other labs -- work in groups of 2-3. • Group lab results presented in class.

  7. Projects • Each group will design an embedded system using a Xilinx FPGA. • Each group will write a paper describing their project. • Each group will give an oral presentation on their project.

  8. Exams • There will be two exams and no final. • Project presentations and demonstrations • Wednesday, April 21th, 7:00 - 10:00 p.m.

  9. Grading • Labs 15% • Projects • Overall design 20% • Written report 10% • Oral presentation 5% • Exam 1 25% • Exam 2 25% • 100%

  10. Office Hours • Tues., Thurs., 2:30 - 3:30 p.m. • Phone: 248-370-2861 • email: haskell@oakland.edu • Web site: • www.cse.secs.oakland.edu/haskell • click on VHDL and CSE 670

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