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Correlated Noise Modeling and Simulation Colin McAndrew, Geoffrey Coram*, Alfred Blaum, Olivier Pilloud Freescale Semico

Correlated Noise Modeling and Simulation Colin McAndrew, Geoffrey Coram*, Alfred Blaum, Olivier Pilloud Freescale Semiconductor *Analog Devices, Inc. Outline. How to simulate noise correlation using the standard SPICE noise analysis How to implement correlated noise in Verilog-A

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Correlated Noise Modeling and Simulation Colin McAndrew, Geoffrey Coram*, Alfred Blaum, Olivier Pilloud Freescale Semico

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  1. Correlated Noise Modeling and SimulationColin McAndrew, Geoffrey Coram*,Alfred Blaum, Olivier PilloudFreescale Semiconductor*Analog Devices, Inc.

  2. Outline • How to simulate noise correlation using the standard SPICE noise analysis • How to implement correlated noise in Verilog-A • Implementing MOSFET induced gate noise in Verilog-A • Physical restrictions on noise geometry scaling • Why Rg/3 works for noise as well as AC

  3. Simulation of Noise Correlation • Can be done with S-parameter or multiport analysis • Not available in all simulators • Is there a simpler approach? That uses the standard SPICE noise analysis? • What if you sum currents? • current: • noise: + = + =

  4. Simulation of Noise Correlation • Consider two “terminal” currents i1 and i2 formed from independent noise currents ia and ib • Form the sum and difference of these currents (easily done with controlled sources in SPICE)

  5. Simulation of Noise Correlation • Standard noise analysis in SPICE gives

  6. Simulation of Noise Correlation • Graphical interpretation: • If perfectly uncorrelated • If perfectly (real) correlated + = + = + = + = 0

  7. Simulation of Noise Correlation • The noise correlation is • and therefore

  8. Simulation of Noise Correlation • This gives the real part of the noise correlation coefficient, what about the imaginary part? • Need to form p/2 phase shifted currents, so multiply by j • This can be done by controlled sources and a capacitor of value C=1/w • Form:

  9. Simulation of Noise Correlation • Graphical interpretation: • If perfectly uncorrelated • If perfectly (imaginary) correlated + = + = + = 0 + =

  10. Simulation of Noise Correlation • Again standard noise analysis in SPICE gives

  11. Correlated Noise Implementation in Verilog-A • Verilog-A is becoming the standard language for compact model definition • There have been on-going questions as to whether it has 100% capability for compact model definition • LRM2.2 specifically targeted language updates to better support compact modeling • The major open question has been: can you implement correlated noise (especially MOSFET gate-drain current noise correlation, which is imaginary valued) in Verilog-A? • Examples to date have shown how to implement cr • We show how to implement c=cr+jci

  12. Correlated Noise Implementation in Verilog-A • The stumbling blocks • correlation analysis requires a p/2 phase shift • this requires a capacitor of value 1/w for implementation • implementation of imaginary correlation therefore can only be done for one frequency • otherwise the correlated noise has to have a (w2) frequency dependence • The “doh!” factor • the primary need at this point for implementation of correlated noise is for gate current noise for MOSFETs • this has an w2 dependence, therefore the “jw” approach for correlated noise implementation actually works perfectly for MOSFET gate current noise

  13. Correlated Noise Implementation in Verilog-A • 2-port correlated noise example 1W 1W want to implement:

  14. Correlated Noise Implementation in Verilog-A • For a 2-port model the basic procedure to follow is: • generate appropriate internal independent noises • use the ddt() operator to implement a p/2 phase shift • this is equivalent to multiplication by jw in AC analysis • i.e. its Fourier transform is multiplication by jw • accept that this gives an w2 frequency dependence to the magnitude of the “induced” noise power spectral density • use appropriated weighted combinations of the internal independent noise sources to implement desired correlation coefficients

  15. Correlated Noise Implementation in Verilog-A • `include "discipline.h" • `include "constants.h" • module correlatedNoise2Port(n1,n2); • inout n1,n2; • electrical n1,n2; • electrical ia,ib; • parameter real c = 0.0 from [0:1]; • parameter real ang = 0.0 from [0:360]; • real cr, ci, cbar, temp; • analog begin • temp = $temperature; • cbar = sqrt(1.0-c*c); • cr = c*cos((ang/180.0)*`M_PI); • ci = c*sin((ang/180.0)*`M_PI); • I(ia)<+white_noise(4*`P_K*temp); • I(ib)<+white_noise(4*`P_K*temp); • I(ia)<+V(ia); • I(ib)<+V(ib); • I(n1)<+V(n1)+ V(ia); • I(n2)<+V(n2)+cr*V(ia)+cbar*V(ib); • I(n2)<+ ddt(-ci*V(ia)); • end • endmodule

  16. Correlated Noise Implementation in Verilog-A • `include "discipline.h" • `include "constants.h" • module correlatedNoise2Port(n1,n2); • inout n1,n2; • electrical n1,n2; • electrical ia,ib;  internal nodes to generate noise on • parameter real c = 0.0 from [0:1]; • parameter real ang = 0.0 from [0:360]; • real cr, ci, cbar, temp; • analog begin • temp = $temperature; • cbar = sqrt(1.0-c*c); • cr = c*cos((ang/180.0)*`M_PI); • ci = c*sin((ang/180.0)*`M_PI); • I(ia)<+white_noise(4*`P_K*temp); • I(ib)<+white_noise(4*`P_K*temp); • I(ia)<+V(ia); • I(ib)<+V(ib); • I(n1)<+V(n1)+ V(ia); • I(n2)<+V(n2)+cr*V(ia)+cbar*V(ib); • I(n2)<+ ddt(-ci*V(ia)); • end • endmodule

  17. Correlated Noise Implementation in Verilog-A • `include "discipline.h" • `include "constants.h" • module correlatedNoise2Port(n1,n2); • inout n1,n2; • electrical n1,n2; • electrical ia,ib; • parameter real c = 0.0 from [0:1];  magnitude of correlation coeff. • parameter real ang = 0.0 from [0:360];  phase of correlation coeff. • real cr, ci, cbar, temp; • analog begin • temp = $temperature; • cbar = sqrt(1.0-c*c); • cr = c*cos((ang/180.0)*`M_PI); • ci = c*sin((ang/180.0)*`M_PI); • I(ia)<+white_noise(4*`P_K*temp); • I(ib)<+white_noise(4*`P_K*temp); • I(ia)<+V(ia); • I(ib)<+V(ib); • I(n1)<+V(n1)+ V(ia); • I(n2)<+V(n2)+cr*V(ia)+cbar*V(ib); • I(n2)<+ ddt(-ci*V(ia)); • end • endmodule

  18. Correlated Noise Implementation in Verilog-A • `include "discipline.h" • `include "constants.h" • module correlatedNoise2Port(n1,n2); • inout n1,n2; • electrical n1,n2; • electrical ia,ib; • parameter real c = 0.0 from [0:1]; • parameter real ang = 0.0 from [0:360]; • real cr, ci, cbar, temp; • analog begin • temp = $temperature; • cbar = sqrt(1.0-c*c);  complement of noise correlation • cr = c*cos((ang/180.0)*`M_PI);  real part of noise correlation • ci = c*sin((ang/180.0)*`M_PI);  imag part of noise correlation • I(ia)<+white_noise(4*`P_K*temp); • I(ib)<+white_noise(4*`P_K*temp); • I(ia)<+V(ia); • I(ib)<+V(ib); • I(n1)<+V(n1)+ V(ia); • I(n2)<+V(n2)+cr*V(ia)+cbar*V(ib); • I(n2)<+ ddt(-ci*V(ia)); • end • endmodule

  19. Correlated Noise Implementation in Verilog-A • `include "discipline.h" • `include "constants.h" • module correlatedNoise2Port(n1,n2); • inout n1,n2; • electrical n1,n2; • electrical ia,ib; • parameter real c = 0.0 from [0:1]; • parameter real ang = 0.0 from [0:360]; • real cr, ci, cbar, temp; • analog begin • temp = $temperature; • cbar = sqrt(1.0-c*c); • cr = c*cos((ang/180.0)*`M_PI); • ci = c*sin((ang/180.0)*`M_PI); • I(ia)<+white_noise(4*`P_K*temp);  1st independent noise source • I(ib)<+white_noise(4*`P_K*temp);  2nd independent noise source • I(ia)<+V(ia); • I(ib)<+V(ib); • I(n1)<+V(n1)+ V(ia); • I(n2)<+V(n2)+cr*V(ia)+cbar*V(ib); • I(n2)<+ ddt(-ci*V(ia)); • end • endmodule

  20. Correlated Noise Implementation in Verilog-A • `include "discipline.h" • `include "constants.h" • module correlatedNoise2Port(n1,n2); • inout n1,n2; • electrical n1,n2; • electrical ia,ib; • parameter real c = 0.0 from [0:1]; • parameter real ang = 0.0 from [0:360]; • real cr, ci, cbar, temp; • analog begin • temp = $temperature; • cbar = sqrt(1.0-c*c); • cr = c*cos((ang/180.0)*`M_PI); • ci = c*sin((ang/180.0)*`M_PI); • I(ia)<+white_noise(4*`P_K*temp); • I(ib)<+white_noise(4*`P_K*temp) • I(ia)<+V(ia);  DC 1W resistor on node ia • I(ib)<+V(ib);  DC 1W resistor on node ib • I(n1)<+V(n1)+ V(ia); • I(n2)<+V(n2)+cr*V(ia)+cbar*V(ib); • I(n2)<+ ddt(-ci*V(ia)); • end • endmodule

  21. Correlated Noise Implementation in Verilog-A • `include "discipline.h" • `include "constants.h" • module correlatedNoise2Port(n1,n2); • inout n1,n2; • electrical n1,n2; • electrical ia,ib; • parameter real c = 0.0 from [0:1]; • parameter real ang = 0.0 from [0:360]; • real cr, ci, cbar, temp; • analog begin • temp = $temperature; • cbar = sqrt(1.0-c*c); • cr = c*cos((ang/180.0)*`M_PI); • ci = c*sin((ang/180.0)*`M_PI); • I(ia)<+white_noise(4*`P_K*temp); • I(ib)<+white_noise(4*`P_K*temp) • I(ia)<+V(ia); • I(ib)<+V(ib); • I(n1)<+V(n1)+ V(ia);  DC 1W resistor plus ia noise • I(n2)<+V(n2)+cr*V(ia)+cbar*V(ib);  DC 1W resistor plus cr noise • I(n2)<+ ddt(-ci*V(ia));  imaginary correlated noise • end (negative sign from c~i1.i2*) • endmodule

  22. MOSFET Induced Gate Noise • Hard to handle in implementation because of the frequency (and bias) dependence • Long channel analysis indicates correlation to drain noise • Naturally follows from distributed (multi-section) analysis • How can gate noise be implemented? • How can this be done efficiently?

  23. MOSFET Induced Gate Noise • Simulation over variations of geometry, bias, and physical parameters shows that • Calculate drain noise current • Implement in two parts • partitioned based on correlation coefficient parameter • Map to gate current using the ddt() operator and parameterized ratio parameter

  24. MOSFET Induced Gate Noise • Reference is symmetric linearized surface potential based model • gets capacitances correct for single section model, with extremely simple form • piece-wise solution for surface potential for simplicity • multiple section (2, 5, 10, 20, 50) simulations done for reference • fT of device is 20GHz • simulations vs. f at Vds=Vgs=2.5V (saturation) • simulations vs. Vds at Vgs=2.5V and f=100MHz

  25. MOSFET Induced Gate Noise • parameter real ci = 0.3987; • parameter real ratio = 0.2755; • real sid, sigrat, qi; • sid = (4.0*`KB*tdevK*mu0*(qi*W*cox)/L); • sigrat= ratio*L*L/(mu0*qi); • I(n) <+V(n); • I(n) <+white_noise(sid); • I(d,s)<+white_noise((1.0-ci*ci)*sid); • I(d,s)<+ci*V(n); • I(g,s)<+ddt(V(n)*sigrat);

  26. MOSFET Induced Gate Noise • parameter real ci = 0.3987;  correlation magnitude • parameter real ratio = 0.2755;  controls magnitude of Sig • real sid, sigrat, qi; • sid = (4.0*`KB*tdevK*mu0*(qi*W*cox)/L); • sigrat= ratio*L*L/(mu0*qi); • I(n) <+V(n); • I(n) <+white_noise(sid); • I(d,s)<+white_noise((1.0-ci*ci)*sid); • I(d,s)<+ci*V(n); • I(g,s)<+ddt(V(n)*sigrat);

  27. MOSFET Induced Gate Noise • parameter real ci = 0.3987; • parameter real ratio = 0.2755; • real sid, sigrat, qi; • sid = (4.0*`KB*tdevK*mu0*(qi*W*cox)/L); drain noise current Sid • sigrat= ratio*L*L/(mu0*qi);  overall ratio Sig/Sid (at w=1) • I(n) <+V(n); • I(n) <+white_noise(sid); • I(d,s)<+white_noise((1.0-ci*ci)*sid); • I(d,s)<+ci*V(n); • I(g,s)<+ddt(V(n)*sigrat);

  28. MOSFET Induced Gate Noise • parameter real ci = 0.3987; • parameter real ratio = 0.2755; • real sid, sigrat, qi; • sid = (4.0*`KB*tdevK*mu0*(qi*W*cox)/L); • sigrat= ratio*L*L/(mu0*qi); • I(n) <+V(n);  DC 1W resistor • I(n) <+white_noise(sid);  “internal” Sid noise • I(d,s)<+white_noise((1.0-ci*ci)*sid); • I(d,s)<+ci*V(n); • I(g,s)<+ddt(V(n)*sigrat);

  29. MOSFET Induced Gate Noise • parameter real ci = 0.3987; • parameter real ratio = 0.2755; • real sid, sigrat, qi; • sid = (4.0*`KB*tdevK*mu0*(qi*W*cox)/L); • sigrat= ratio*L*L/(mu0*qi); • I(n) <+V(n); • I(n) <+white_noise(sid); • I(d,s)<+white_noise((1.0-ci*ci)*sid);  drain noise current, part 1 • I(d,s)<+ci*V(n);  drain noise current, part 2 • I(g,s)<+ddt(V(n)*sigrat);

  30. MOSFET Induced Gate Noise • parameter real ci = 0.3987; • parameter real ratio = 0.2755; • real sid, sigrat, qi; • sid = (4.0*`KB*tdevK*mu0*(qi*W*cox)/L); • sigrat= ratio*L*L/(mu0*qi); • I(n) <+V(n); • I(n) <+white_noise(sid); • I(d,s)<+white_noise((1.0-ci*ci)*sid); • I(d,s)<+ci*V(n); • I(g,s)<+ddt(V(n)*sigrat);  gate noise current

  31. MOSFET Induced Gate Noise • There is one subtle problem with this model:It is not properly symmetric! • At Vds=0 there should be no “preference” for the induced gate noise to flow gate-source compared to gate-drain • The induced gate noise arises from capacitive coupling from channel thermal noise to the gate • Intuitively, partitioning of the gate noise current between source and drain should depend on the relative source and drain charges or capacitances

  32. MOSFET Induced Gate Noise • parameter real ci = 0.3987; • parameter real ratio = 0.2755; • real sid, sigrat, qi, qs, qd; • sid = (4.0*`KB*tdevK*mu0*(qi*W*cox)/L); • sigrat= ratio*L*L/(mu0*qi); • I(n) <+V(n); • I(n) <+white_noise(sid); • I(d,s)<+white_noise((1.0-ci*ci)*sid); • I(d,s)<+ci*V(n); • I(g,s)<+ddt(V(n)*sigrat*qs/qi);  gate-source noise current • I(g,d)<+ddt(V(n)*sigrat*qd/qi);  gate-drain noise current

  33. MOSFET Induced Gate Noise

  34. MOSFET Induced Gate Noise

  35. MOSFET Induced Gate Noise

  36. MOSFET Induced Gate Noise

  37. MOSFET Induced Gate Noise • NOTE: an empirical correction was added to get the Vds dependence of the correlation • without this it did not approach zero as Vds→0 • The Vds dependence of the gate and drain noise current magnitude follows naturally from the form of the model • The frequency dependence of the real and imaginary parts of the correlation coefficient are qualitatively and quantitatively reasonable up to about fT • this was not planned, it serendipitously followed from introducing source-drain symmetry • especially note the behavior of the real part of the correlation coefficient, which deviates from the “ideal” behavior at lower frequency than does the imaginary part

  38. MOSFET Induced Gate Noise

  39. Noise Geometry Scaling • Many forms have been proposed • MOS 1/f: • MOS thermal: • Resistor:

  40. Noise Geometry Scaling • Fundamental equivalents L 2x L/2,W W 2x L,W/2

  41. Noise Geometry Scaling • Assume: (or gm in place of I) • For two L/2 devices in series, width and current (or gm) are the same for each segment, the short-circuit noise current from each segment splits between “internal” and “external” routes, for a ¼ transfer to total noise current, and there are two independent noise sources:

  42. Noise Geometry Scaling • For two W/2 devices in parallel, width and current (or gm) are halved for each segment, the short-circuit noise current from each segment directly add to total noise current, and there are two independent noise sources:

  43. Noise Geometry Scaling • Inescapable implication of basic physical requirements • This is for “linear,” not “saturation,” operation • Similar results holds for “area” dependent devices • BJTs and diodes • Experiments supporting this imply assumptions of spatial uniformity and no correlation are correct

  44. Noise Geometry Scaling • Thermal noise is independent of current, A=0 • Consistent with resistor thermal noise, GW/L • Consistent with MOSFET thermal noise, |Qi|/L2W/L • 1/f noise varies as 1/WL • “averaging” occurs over device area, like mismatch • only if current (conductance) coefficient is A=2 • “Intuitive” introduction of A2 is incorrect • basic flaw in many SPICE noise models

  45. Distributed RC System • For a distributed RC system, for low frequency AC: • (this follows from equating transmission line analysis to the first order lumped element equivalent)

  46. Distributed RC System • N-sectionsimulationsshows asN→ the(low freq.)noise currentis correctlymodeled by • Rg/3 in series • with C • Why?

  47. Distributed RC System • Consider a section dy

  48. ~ Distributed RC System • Noise voltage from this section is 4kTRgdy/W

  49. ~ Distributed RC System • Analysis with a TL model substituted for each segment shows that “open end” capacitance is dominant term

  50. Distributed RC System • Integrating over the whole width • Therefore Rg/3 in series with C gives proper modeling of noise as well as AC behavior (for low frequencies)

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