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Advanced Implantation Detector Array (AIDA): Update & Issues

Explore the latest advancements and challenges in the AIDA collaboration's implantation detection system presented by Tom Davinson. Learn about the prototype AIDA ASIC design and functionality.

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Advanced Implantation Detector Array (AIDA): Update & Issues

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  1. Advanced Implantation Detector Array (AIDA): Update & Issues presented by Tom Davinson on behalf of the AIDA collaboration (Edinburgh – Liverpool – STFC DL & RAL) Tom Davinson School of Physics & Astronomy The University of Edinburgh

  2. Prototype AIDA ASIC: Channel Layout • High (20MeV FSR), intermediate (1GeV FSR) and low gain (20GeV FSR) channels in parallel • Blocks are sequenced to follow signal’s flow (“left to right”) • Shaper and peak hold at back end to minimize noise • 400mm x 6mm Peak Holds + MUX Fast comparators High speed buffer Slow comparator 700pF feedback capacitor Shapers Preamplifiers + feedback 400mm ~6mm

  3. Prototype AIDA ASIC: Top level design • Analogue inputs left edge • Control/outputs right edge • Power/bias top and bottom • Prototypes delivered May 2009 MPW run 100 dies delivered • Functional tests at STFC RAL OK

  4. Prototype AIDA ASIC: Analogue input and bias reference

  5. Prototype AIDA ASIC: Analogue outputs

  6. Prototype AIDA ASIC

  7. 1: Medium Energy (ME) + ME Input signals (voltage step capacitive-coupled) Preamp buffered output (Low-Medium Energy Channel) Trigger output “Data Ready” signal Variable medium-energy (ME) event followed after 5us by a second fixed ME event: the energy of the first event (11.75pC, 23.5pC, 35.25pC) does not affect the response to the second (11.75pC).

  8. 1: Medium Energy (ME) + ME Input signals (voltage step capacitive-coupled) Analog output (peak-hold multiplexed output) Trigger output “Data Ready” signal When the data ready signal is active, the correct value is present at the analogue output (after the hit has been detected and the correct address been fed into the output multiplexer). NB: the test environment is very noisy and that affects the measurements.

  9. 2: High Energy (HE) + ME Input signals (voltage step capacitive-coupled) Preamp buffered output (Low-Medium Energy Channel) “Range” signal High = high-energy channel active “Data Ready” signal Three high-energy (HE) events (610pC, 430pC, 250pC) followed by a ME event (28.8pC): the initial HE event does not affect the response to the second. [The roll-of of the L-ME channel preamplifier is due to the HE channel amplifier becoming active: the two are effectively in parallel. Note the Range signal changing status after the HE event]

  10. 2: High Energy (HE) + ME Preamp buffered output (Low-Medium Energy Channel) Analog output (peak-hold multiplexed output) “Data Ready” signal Although the low-medium energy channel preamp saturates, the correct value is stored and multiplexed to the Analog Output when the “Data Ready” signal is active.

  11. 3: High Energy (HE) + ME Input signals (voltage step capacitive-coupled) Preamp buffered output (Low-Medium Energy Channel) “Range” signal High = high-energy channel active “Data Ready” signal Fixed high-energy (HE) event (610pC) followed by three ME events (15pC, 30pC, 45pC): the ASIC recovers autonomously from the overload of the L-ME channel and the second event is read correctly.

  12. 3: High Energy (HE) + ME Input signals (voltage step capacitive-coupled) Analog output (peak-hold multiplexed output) “Range” signal High = high-energy channel active “Data Ready” signal First value (constant) given by the High-Energy channel, second by the Medium-Energy channel.

  13. Prototype AIDA Mezzanine • 4x AIDA ASICs 64 channels • Design complete • Delivery end-October 30 units 3rd September 2009

  14. Prototype AIDA FEE FPGA, Memory, Gbit Digital readout Multiplex readout Power Supplies Clockdistribution Mezzanine • Design complete • Production in progress • 8 units (4x AIDA, 2x DL DDG, 2x LYCCA) • Delivery w/c 21.9.09

  15. Prototype AIDA FEE:

  16. FEE Assembly Sequence

  17. Prototype AIDA Enclosure • Prototype mechanical design • Based on 8cm x 8cm DSSSD • evaluate prior to design for 24cm x 8cm DSSSD • Compatible with RISING, TAS, 4p neutron detector • 12x 8cm x 8cm DSSSDs • 24x AIDA FEE cards • 3072 channels • Design complete • Mechanical assembly in • progress

  18. Prototype AIDA Enclosure

  19. AIDA Project Timeline • November/December 2009 • Systems integration (ASIC+Mezzanine+FEE) • Bench tests • February 2010 • In-beam tests • March 2010 • Design revisions • April 2010 • ASIC wafer run • FEE production run • June 2010 • Production delivery complete

  20. AIDA Project Information Project web site http://www.ph.ed.ac.uk/~td/AIDA/welcome.html Design Documents http://www.ph.ed.ac.uk/~td/AIDA/Design/design.html Technical Design Review v1.1 ASIC Project Specification v1.4 FEE Specification v1.0 The University of Edinburgh (lead RO) Phil Woods et al. The University of Liverpool Rob Page et al. STFC DL & RAL John Simpson et al. Project Manager: Tom Davinson

  21. Acknowledgements This presentation includes material from other people My thanks to: Ian Lazarus, Patrick Coleman-Smith, Jonathan Strachan & Paul Morrall (STFC DL) Steve Thomas & Davide Braga (STFC RAL) Zhong Liu (Edinburgh) Dave Seddon, Sami Rinta-Antila & Rob Page (University of Liverpool)

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