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Introduction to Controlling the Output Power of a Transistor Stage

Introduction to Controlling the Output Power of a Transistor Stage. A load network will be designed to maximize the output power obtainable from the Mitsubishi MGF0909A power transistor. The gain associated with maximum power is high enough not to be a concern in this case.

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Introduction to Controlling the Output Power of a Transistor Stage

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  1. Introduction to Controlling the Output Power of a Transistor Stage A load network will be designed to maximize the output power obtainable from the Mitsubishi MGF0909A power transistor. The gain associated with maximum power is high enough not to be a concern in this case. Two solutions to the matching problem will be considered. The network selected will be expanded to allow for feeding the required dc to the drain of the transistor. Care will be taken to model the effects of the high Q capacitors added accurately. Changes will also be made to the matching network to reduce the expected discontinuity effects and the network will be optimized to restore the power performance.

  2. The circuit as set up in the previous example.

  3. The CIL Command is selected on the left (Synthesis Toolbar) to control the output power of the transistor.

  4. The matching network required will be inserted at the position shown.

  5. The CIL Wizard has been launched.

  6. The passband can be modified on this page.

  7. The option to control the output power has been selected.

  8. The S-parameter normalization resistance can be changed here.

  9. The actual output power and the operating power gain are of interest. Power contours will be generated.

  10. The power targeted must be specified on this page

  11. The Display Contours Command has been selected.

  12. The zoom slider was used to expand the view around the optimum power load.

  13. The maximum power is targeted. Additional contours can be displayed at 1dB and 2dB down from the optimum.

  14. The performance around the power contour targeted is tabulated at 2.075GHz. The optimum point on the contour is high-lighted and can be changed at this point.

  15. The terminations to be presented by the matching network in order to realize the power targeted are tabulated here.

  16. The Display Impedance Radio Button was selected to list the impedance required for maximum output power (the power targeted).

  17. The default name assigned to the data file of the matching problem to be solved.

  18. The final page of the Power Contour Wizard.

  19. The Impedance-Matching Module has been activated. The problem will be solved with a non-commensurate microstrip network.

  20. The Distributed Network Wizard will be launched to set the constraints on the microstrip networks to be synthesized.

  21. The general form of the non-commensurate networks allowed is displayed.

  22. The specifications of the substrate to be used.

  23. The specifications of the via holes to be used.

  24. The parasitic inductance for any capacitors to be used (0603).

  25. Double stubs and stepped main-line sections will be allowed.

  26. The line widths and the stub separation to be used.

  27. A rendering of the specifications made.

  28. The parasitics associated with the T-junctions associated with the specifications made.

  29. The default gaps to be used for any capacitors or inductors.

  30. The pad size to be used for any series capacitors.

  31. The electrical line length of the pads should be kept short.

  32. The steps of the wizard have been completed.

  33. The changes made must be saved before the synthesis cycle is started.

  34. The Synthesis Command is selected.

  35. The synthesized solutions can be optimized for the best active performance.

  36. The optimization target selected for the output power is the same as before.

  37. The gain targeted is also the same as before.

  38. Different weights can be assigned to the output power and the gain targeted.

  39. The best solution (smallest error) obtained with the specifications made.

  40. The impedance presented to the circuit by the selected matching network.

  41. An exploded view of the power termination.

  42. The command to display the active performance associated with the selected solution.

  43. The output power and gain associated with the selected solution.

  44. The artwork of the solution.

  45. The solution will be closed and alternatives will be investigated.

  46. The Specifications | Topology Command will be selected.

  47. The option not to use any series capacitors will be explored.

  48. Solutions without any series capacitors will be synthesized.

  49. The option to optimize the active performance will be selected again.

  50. The same power target is used again.

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