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CSET 4650 Field Programmable Logic Devices

VHDL Counters. CSET 4650 Field Programmable Logic Devices. Dan Solarek. E . E . E . E. E. Reset. E. E . E . E. E . E. E. E. Counters. Any sequential circuit whose state diagram is a single cycle. Ripple Counters. Uses trigger or “T” flip-flops

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CSET 4650 Field Programmable Logic Devices

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  1. VHDL Counters CSET 4650 Field Programmable Logic Devices Dan Solarek

  2. E E E E E Reset E E E E E E E E Counters • Any sequential circuit whose state diagram is a single cycle.

  3. Ripple Counters • Uses trigger or “T” flip-flops • Each flip-flop acts as a “divide-by-two” with respect to the CLK input • Count ripples through the flip-flops

  4. Ripple Counter Timing

  5. LSB Serial enable logic MSB Synchronous Counters • Synchronizing the flip-flops with the clock assures that all change together

  6. LSB Parallel enable logic MSB Synchronous Counter • A parallel version of the synchronous counter

  7. 74x163 MSI 4-Bit Counter

  8. 74x163 Internal Logic Diagram • XOR gates embody the “T” function • Mux-like structure for loading

  9. Counter Operation • Free-running 16 • Count if ENP andENT both asserted. • Load if LD is asserted(overrides counting). • Clear if CLR is asserted (overrides loading and counting). • All operations take place on rising CLK edge. • RCO is asserted if ENT is asserted and Count = 15. Lect #12 Rissacher EE365

  10. Free-Running 4-bit ’163 Counter • Timing diagram for a “divide-by-16” counter Lect #12 Rissacher EE365

  11. 4-Bit Binary Counter • VHDL for a 4-bit binary counter • Behavioral architecture library ieee; -- A four-bit counter. use ieee.std logic 1164.all; use ieee.std logic unsigned.all; entity count4 is port(Resetn, E, clk : in STD_LOGIC; Q : out STD_LOGIC_VECTOR (3 downto 0)); end count4; architecture Behavior of count4 is signal Count : STD_LOGIC_VECTOR (3 downto 0); begin process (clk, Resetn) begin if Resetn = '0' then Count <= "0000"; elsif (clk'EVENT and clk = '1') then if E = '1' then Count <= Count + 1; end if; end if; end process; Q <= Count; end Behavior;

  12. 4-Bit Binary Counter • VHDL for a 4-bit binary counter • Behavioral architecture library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; --to get arithmetic operations entity counter4 is port( CLK, CLR_L: in STD_LOGIC; Q: out UNSIGNED(3 downto 0); end counter4; architecture counter4_arch of counter4 is signal IQ: UNSIGNED (3 downto 0); --Internal counter state begin process ( CLK, IQ ) begin if (CLK'event and CLK='1') then -- Rising edge of clock if CLR_L='0' then IQ <= (others => '0'); --Synchronous Reset else IQ <= IQ + 1; --Increment count end if; end if; Q <= IQ; -- Output end process; end counter4_arch;

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