1 / 7

Jon Andrews Supervisor: J Garside

My Little Computer. Jon Andrews Supervisor: J Garside. Project Outline: To implement a real commercial processor into an Field Programmable Gate Array (FPGA). It should be able to run code from the original processor. Processor: 8080, 6800, 6502, PDP-8 Digital Equipment Corporation PDP-8:

sopoline-morrow
Download Presentation

Jon Andrews Supervisor: J Garside

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. My Little Computer Jon AndrewsSupervisor: J Garside • Project Outline:To implement a real commercial processor into an Field Programmable Gate Array (FPGA). It should be able to run code from the original processor. • Processor: 8080, 6800, 6502, PDP-8 • Digital Equipment Corporation PDP-8: • 12 Bit CISC Machine4K Words of Memory8 Basic InstructionsOperating System DEC OS/8 • History • 100,000 Machines SoldPDP-8/I Introduced in 1968Last Machine Built In 1984 (PDP-8/A) PDP-8 Jon Andrews

  2. Instruction Set • Instructions • AND, TAD, ISZ, DCA, JMP, JMS, IOT, OP • Instruction Set Format: • 3 Bits for Opcode 7 Bits for address • 12-bit Memory Location is Inferred • Key Features • Jump to Sub Routine • Return Address Stored in 0 • Auto Indexing • Instruction Set Flow Control (no conditional branch) • 13 Microcoded Instructions Page Layout 12 Bits Page 0 Page 1 Page 32 Page 31 PDP-8 Jon Andrews

  3. 12 Bits 1001 5212 1741 1001 1742 1743 ADD I 141 Example Instruction • E.G. 001 11 11000012 AT Location 17438 • Instruction: Two’s Complement ADDIndirect Bit: ‘1’Page Bit: ‘1’Page Offset: ‘1100001’EA: (17418) = 10018CA: (10018) = 52128 • This will give AC <- AC + 52128 PDP-8 Jon Andrews

  4. Processor Operation • Original PDP-8 • 7 Fetch States • 6 Executions States • 1 IDLE State • Total 14 States • My Implementation • 5 Generic States • Reasons For Reduction • Larger Transistor Budget • Ability to Operations in Parallel • Faster Memory • More Buses PDP-8 Jon Andrews

  5. State Diagram IDLE • F0 • Start State • Loop in this state when IDLE • F1 • Address of Operand Calculated • F2 • Address Read from operand to fetch indirected data • E0 • Instruction execution, eg ADD • Loop in this state when microcoded instruction being processed • E1 • Updates the Auto Index value of memory F0 Instructions Fetched Execution Complete Microcode Incomplete F1 E0 Get Operand (Direct) Auto Index Written to Memory (deferred) Get Operand Get Operand (InDirect) Get Operand Addr (InDirect) F2 E1 Auto Index Calculation PDP-8 Jon Andrews

  6. Conclusion • Change in design due to technology • Move towards RISC • Single Cycle Execution • Register-Register, not Memory • More Functionality now introduced • Sub, Multiply • Increased performance • Cycle time can be reduced due to the speed of electronics • Execution states dramatically reduced Time Scale • Data Path Mid Nov • ALU + functional blocks End Nov • Control End Dec • Test Programs End Feb • Time Permitting • I/O Interface • Focal PDP-8 Jon Andrews

  7. Data Path PDP-8 Jon Andrews

More Related