912.001 Layout Planning of Mixed-Signal Integrated Circuits Chung-Kuan Cheng / Andrew B. Kahng UC San Diego CSE Departm

1. 912.001 Layout Planning of Mixed-Signal Integrated CircuitsChung-Kuan Cheng / Andrew B. KahngUC San Diego CSE Department

2. Planning Goals Timing Power Feasibility Elements Blocks Power/Ground Clocks Buses Resources Silicon Routing layers

3. Mixed-Signal Planning Goals Timing Power Feasibility Elements Blocks Power/Ground Clocks Buses Resources Silicon Routing layers Unified and constrained: (1) polygon- and die-level optimizations; (2) device / interconnect embedding; (3) performance analysis and layout synthesis

4. Mixed-Signal Planning Scope System Geometry, Wires Architecture RF, Analog Digital Floorplan Logic Feasibility, Performance Layout

5. Initial Project Activities • Useful Background • Interconnect synthesis (P/G, clock, signal topology) and RLC analysis (book,glossary) • Multilevel optimizers since 1995: partitioning (MLPart), placement (Capo, CapoT) • Primal-dual optimization frameworks • Floorplan representations and optimizations: O-tree, corner block list, … + compaction • M/S Context • Circuit/System types • Constraint types • Figures of merit • Design/layout best practices M/S Planning Capability Develop • Layout Representation • Devices, interconnects both first-class citizens • System-level interconnect synthesis (e.g., arch / “cells”) • Hybridization of topological, spatial representations • Digital + A/MS Integration • Power • Isolation • Technology (device and interconnect variability, heterogeneous integration) Leverage • Students, Faculty • Bo Yao (PhD 2005), Mingyuan Li (PhD 2006) • C.-K. Cheng, Andrew Kahng Use Model • Constraint-Dominated Optimization • Scalable, high-quality • Focus on mixed-mode embedding, “primal-dual” opt Understand

6. Mixed-Mode Embedding • Traditional blocks • Traditional cells • Mixed-Mode (blocks + cells) • Mixed-Signal • RF, Analog, Digital Modules + Wires

7. Mixed-Mode: Blocks and Cells

8. Hierarchy Management/Reconciliation “Layout Tree” “Design Tree”

9. Traditional Context: Digital Control logic allowed to overlap because these are regions, not exact placements of hard cells. Control Datapath High regularity of datapath logic DP, repeaters, clock buffers, memory, BIST,…

10. “Classical Floorplanning Harmful” tutorial slide, ISPD April 2000 http://vlsicad.ucsd.edu/papers/slides/ispd00-cfh.ppt

11. Cell Placement • (Commoditized) • Based on: • Multi-level clustering (RTL hierarchy-aware, HEM, PinHEM, HEC, Rent-based, etc. etc. etc. variants) • Hybrid of analytic and partitioning methods • Bundled with incremental STA, basic timing/SI-driven opts • Assume can leverage existing, foreseen technology • SPC, Cadence/Avant!/Mentor, Synopsys/Magma, … • Capo, CapoT, Dragon, Mongrel, Feng Shui (various LEF/DEF compatible open-source placers in MARCO GSRC Bookshelf)

12. Block Placement

13. O-Tree Representation • Representation = key issue • Cover all kinds of floorplans • Easy to manipulate • O-tree = good candidate • Covers both slicing and non-slicing • O(n) time to derive the floorplan • Handles various constraint types, e.g., symmetry • Tree structure  easy to represent interconnect channels • Current goal: Equal representation of both “modules” and interconnects

14. Analog Layout Issues • Power, ground, guard ring design • Centering (thermal, process,…) • Matching issues • Area: manage relative impact • Distance: match environment effects • Shape, orientation: match process distortions • Symmetry: differential signaling • Constraints • Parasitics: diffusion parasitic C, R; inductance (high-freq); interconnect coupling) • Geometry: fixed locations, ARs/dimensions • Isolation • Substrate noise: distance, guard rings • Thermal variation: distance from hot spots • Power supply distribution

15. RF Layout Issues • Power/Ground • EMI • Main goal = performance • RF design is wire-dominated • Precise wire topology, length • Planar layout • Cf. Aktuna/Rutenbar 1999

16. Sensitivities and Primal-Dual Framework • Planning tools must understand sensitivities • Buffer insertion, gate sizing, replication • Wire sizing, shielding, signaling architecture • Primal: • Timing, routing completion, … • Dual: • Net cost, path cost, routing area cost, placement location cost, … • Experience with e.g., provably good primal-dual approximations for multi-commodity flow (ICCAD00, ASPDAC01, ASPDAC02)

17. SPARE SLIDES

18. Example Planning Issue: P/G Distribution

19. Example Planning Issue: Clock Distribution

20. Floorplan Representations Slicing Ordered Tree Sequence Pair Corner Block List Twin Binary Tree Ordered Tree

21. A E D B F C Slicing Floorplan colors of adjacent nodes differ D F E Slicing Ordered Tree A C B

22. F C E A E B B C A 0 X D X 1 X D A D E 1 F B F 0 1 X C 0 1 0 0 1 Twin Binary Trees (1)=11001 (2)=00110 order(t1)=order(t2)=ABCDFE

23. B C A B C D A D F E E F O-Tree SP1=(ABCDFE,FADEBC) SP2=(ABCDFE,FADBEC) CBL=(FADEBC,11101,0010100) CBL90=(ABCDFE,00110,00101010)

24. Relations Between Representations 900 O-tree T SP (s1,s2) TBT (t+,t-) CBL (S,L,T) tree transform sequence