Unit-4: I/O Techniques

1. Unit-4: I/O Techniques Prof.M.RajasekharaBabu School of Computing Science and Engineering mrajasekharababu@vit.ac.in

2. OutLine • Recap • SessionObjectives & Teaching Learning Material • Session Plan • Bus Arbitration • Memory Maped I/O • Isolated I/O • Polling • Assignment • References

3. Re-Cap 1. List few hard errors in semiconductor memories 2. Tell reasons for soft errors in Semiconductor memories 3. What is the disadvantage of Hamming Code? 4.Distingush between Evan Parity and Odd Parity 5. In error correcting code function, when the word is fetched a new code is generated and compared to the _______ code.

4. Objectives & Teaching Learning Material • Session Objectives • To provide knowledge on how to find errors in semiconductor memory and correct them • Teaching Learning Material • LCD, White board Marker, Presentation slides

5. Session Plan

6. Bus Arbitration • More than one module controlling the bus • e.g. CPU and DMA controller • Only one module may control bus at one time • The bus master (bus controller) needs a way to select one of the units. This selection process is called Bus arbitration • Three different arbitration schemes: (number of control lines, speed of bus controller) • Daisy chaining • Polling • Independent requesting • Some bus systems combine several distinct arbitration techniques

7. Bus Arbitration Types of Arbitration: static: (priority fixed) dynamic: (flexible priority) - Daisy chaining - polling - Parallel arbitration -Time slice - Independent Requesting. -LRU/FIFO - rotating daisy chain Arbitration may be centralised or distributed

8. Centralised or Distributed Arbitration • Centralised • Single hardware device controlling bus access • Bus Controller • Arbiter • May be part of CPU or separate • Distributed • Each module may claim the bus • Control logic on all modules

9. A centralized bus arbiter using daisy chaining

10. U1 U2 Un Bus Controller … Poll Count Bus Bus Request Bus Busy Polling

11. polling • Unit requests the bus via BUS request line. • In response, the Bus controller proceeds to generate a sequence of numbers on the poll-count lines. • Each unit compares to the unique address assigned to it. • When requesting unit finds the match, Bus Busy signal is activated. • In response, bus controller terminates the polling process and Ui connects to the bus. • Advantage: failure of one unit need not affect the other units. • Disadvantage: expensive because of more control lines. Number of units are limited based on the poll-count lines capability

12. U1 U2 … Un Bus Grant1 Bus Controller Bus Request1 Bus Grant2 Bus Request2 Bus Grant n Bus Request n Bus Busy Bus Independent Requesting • The bus controller determines priority, which is programmable. • Drawback: 2n Bus request and bus grant lines to control n devices, whereas daisy chaining requires 2 such lines and polling requires log2n lines approximately.

13. Role of CPU in transfer of information peripheral device -> CPU -> memory • CPU limits the speed of transfer Peripheral device -> memory • Transfer speed increases • Peripheral device manage the memory bus directly. • DMA (Direct memory Access) • CPU is idle

14. CPU Bus Signals for DMA Transfer • DMA Controller sends Bus Request to CPU • CPU stops execution of current instruction and places address bus, data bus, read and write lines into high impedance state. • CPU activates Bus Grant • After transfer DMA disables BR • CPU continues normal operation

15. Different ways of DMA transfer • Burst transfer – a block sequence consisting of a number of memory words is transferred in a continuous burst => need for fast devices • Cycle stealing – transfer one word at a time, after which it must return control of the buses to the CPU. • CPU delays 1 cycle to allow Direct Memory I/O transfer

16. References • M. M. Mano, Computer System Architecture, Prentice-Hall • William Stallings “Computer Organization and architecture” Prentice Hall, 7th edition, 2006