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UA9 Telescope DAQ

UA9 Telescope DAQ. J. Fulcher Imperial College. DAQ Basics. Based upon slice of CMS Tracker DAQ ~ 1/440 of Tracker DAQ All subsystems used except: FEC CCU rings FMM FRL These are replaced by: Vi2c card to program the modules Simple electrical clock distribution

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UA9 Telescope DAQ

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  1. UA9 Telescope DAQ J. Fulcher Imperial College Jonathan Fulcher

  2. DAQ Basics • Based upon slice of CMS Tracker DAQ • ~ 1/440 of Tracker DAQ • All subsystems used except: • FEC • CCU rings • FMM • FRL • These are replaced by: • Vi2c card to program the modules • Simple electrical clock distribution • Home cooked trigger card for trigger rules and backpressure handling • FedKit Slink readout Jonathan Fulcher

  3. First Test Beam • VME readout • Trigger rate limited to 600 Hz • Due to limitations in FED VME readout • Plan for September test • S-Link readout • Expected trigger rate up to 10kHz Jonathan Fulcher

  4. CMS Tracker Readout System Jonathan Fulcher

  5. Control and Readout System 10 sensors Telescope has 30 channels ~ 7680 strips in 5 planes 60 APVs 30 Fibres Vi2c 1 FED Jonathan Fulcher

  6. Trigger Full System Setup TTCci TTS Compact PCI crate FED crate FE modules FED Kit Vi2c FED i2c DAQ PC Jonathan Fulcher

  7. FED 9U Board • 9U VME64x • PCB 14 layers (incl 6 power & ground) • ~ 6 K components (smallest 0402) ; ~ 25 K tracks • BGAs largest 676 pins @ 1 mm pitch • 96 ADC channels : • AD9218 Dual package 10 bit @ 40 MHz • Half Analogue circuitry on Secondary Side • JTAG Boundary Scan Jonathan Fulcher

  8. 12 12 12 12 12 12 12 12 FED Overview Modularity 9U VME64x Form Factor Modularity matches Opto Links 25,000 Si strips / FED 1 FED in Total. Up to 8 x Front-End “modules” OptoRx/Digitisation/Cluster Finding Back-Endmodule / Event Builder VME module / Configuration Power module Other Interfaces: TTC : Clk / L1 / BX DAQ : Fast Readout Link TCS : Busy & Throttle VME : Control & Monitoring JTAG : Test & Configuration 96 Tracker Opto Fibres CERN Opto- Rx 9U VME64x Analogue/Digital JTAG FPGA Configuration Compact Flash FE-FPGA Cluster Finder VME Interface VME-FPGA BE-FPGA Event Builder TCS TTC TTCrx DAQ Interface Buffers Power DC-DC Temp Monitor Jonathan Fulcher Front-End Modules x 8 Double-sided board Xilinx Virtex-II FPGA TCS : Trigger Control System

  9. Firmware and FPGAs Delay x 24 FE x 8 Baseline of 4 FPGA Final Designs working... VME x 1 BE x 1 34 Xilinx Virtex II FPGAs up to 2M equiv gates each Delay FPGA: ADC Coarse and Fine Clock Skewing. FE FPGA: Scope and Frame Finding modes. BE FPGA: Event building, buffering and formatting. VME FPGA: Controls and Slow Readout path. Jonathan Fulcher

  10. S-LINK VME Transition Card • Simple 6U board: • Provides interface between FED and Slink Transmitter • Provides access to FED Throttle signals VME Backplane Slink Transition Card FED Slink Data & Control Signals DAQ Slink Transmitter 6U FED Throttle Signals Ethernet Connector Jonathan Fulcher

  11. Optical Analogue Links • Data from the Tracker Front-End is transferred over analogue optical links. • 2 APV25 data frames per optical channel • Analogue link gain is set to 1 • Handling of zero suppression off-detector allows more flexibility for algorithm adjustment and common mode subtraction handling • 30 links carry ~ 3 Mbytes / s each @10kHz • Factor 100 gained in Zero Suppression Jonathan Fulcher

  12. Example 2xAPV25 Multiplexed Data Frame Jonathan Fulcher

  13. Fed Data Handling • Fed buffer interpreted by specialized c++ unpacker class within CMSSW • Runs with thorough checking or streamlined data access modes • Full data integrity self check • Access to all data in header and payload • Completely integrated within CMSSW Jonathan Fulcher

  14. Run Control • User logs onto a webpage • Selects the configuration he wants to run • He instantiates that configuration, this then launches all the web servers on the specified machines for that configuration and loads all the XDAQ Applications • He is then in a position to use the run control to issue the state transition commands to all the XDAQ Applications in that configuration. • Once you start the config the FED is ready to take data, it remains only for the triggers to arrive. Jonathan Fulcher

  15. Data Handling in XDAQ • Standard Filter Unit and Storage Manager from CMS are used • Goniometer Control in XDAQ application • Data Analysis performed in CMSSW • Fast feedback from analysis to Gonio • Mark P will present more… Jonathan Fulcher

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