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This chapter covers various topics in combinational circuit design, including compound gates, asymmetric gates, cascade voltage switch logic (CSVL), and dynamic circuits. It discusses the advantages and disadvantages of these circuit designs, as well as common problems and solutions. Topics covered include pseudo-nMOS, dynamic gates, domino gates, pass-transistor circuits, and back-gate coupling.
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Chapter 6 Combinational Circuit Design
Asymmetric Gates Cap on the input A is (2+4/3)=10/3 Logical effort=(10/3)/3=10/9 Better than Normal NAND gates (4/3) To optimize for the input-to-output delay
Pseudo-nMOS Pseudo-nMOS works well for wide NOR structures than NAND structures HW. 6.19
Cascade Voltage Switch Logic (CSVL) Advantages: 1. Without the static power consumption 2. Due to logic with nMOS, the speed can be improved 3. The input capacitance is reduced 4. Require the complement logic HW. 6.26
Footed and Unfooted DG To ovoid error contention during precharge phase
Dynamic Gates Advantages: 1.Zero static power consumption 2. Fastest circuit family Disadvantages: • Require Clocking • Consume dynamic power consumption 3. Sensitive to noise
Domino Gates Inherent non-inverting
Keepers DG suffers from charge leakage on the dynamic node. Keeper is a weak MOS that holds the output at the correct level when it floats.
Ratio Failures Weak transistor must be sufficiently small that the output level falls below VIL of the next stage
Power Supply Noise IR drop and di/dt noise cause noise margin problems and degrade delay margins
Back-gate Coupling Resulting in a droop on the dynamic node X