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Sequential Circuits: Implementation and Applications

Explore the classification, implementation, and applications of sequential logic circuits, including RS flip-flops and clock signals. Learn about synchronous and asynchronous systems.

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Sequential Circuits: Implementation and Applications

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  1. Sequential Circuits Lect#7

  2. Sequential Logic These systems find wide application. • In implementing systems with a sequence of events such as an industrial process control system. This implies that such systems 1.   Must have a synchronising signal, i.e. a clock signal 2.   Must remember where we are in the sequence requires a memory

  3. Sequential Logic

  4. Synchronous and Asynchronous There are two classes/types of Sequential Logic • classification depending on the timing of the signals. • Synchronous a synchronous sequential circuit is a system whose behaviour can be defined from a knowledge of its signals at discrete instants of time. • Asynchronous the behaviour of an asynchronous sequential circuit depends upon the order in which the input signals change and can be affected at any instant of time.

  5. RS Flip-Flop The device is said to be: ·       SET when Q output = 1 And ·       RESET when Q output = 0

  6. Implementation of RS Flip-Flop RS-flip-flops can be formed from either ·       two NAND gates or ·       two NOR gates. • The cross-coupling from the output of one gate to the input of the other gate constitutes a feedback path.

  7. RS Flip-Flop • Both inputs remain at 0 normally until state of flip-flop has to be changed Recall that • the output of a NOR = 0 if any input = 1 • the output of a NOR = 1 if both/all inputs = 0

  8. RS Flip-Flop 1. As an initial condition assume that S = 1 and R = 0.  since Gate 2 has an input = 1   both inputs to Gate 1 = 0  2. when S = 0  the outputs remain the same because remains =1  leaves one input to Gate 2 = 1  remains = 0  both inputs to Gate 1 remain = 0 

  9. RS Flip-Flop 3. Similarly, it is possible to show that a 1 at the Reset input  changes  4. When the Reset input returns to zero  the outputs do not change Another Implementation can be with NAND gates  Both inputs remain at 1 normally until state of flip-flop has to be changed. NOTE : the position of S and R

  10. RS Flip-Flop with EN/CP  Can also have an implementation with an enable/clock If the En/Cp =0 • device is not active • the outputs of the NAND’s remain at logic level 1 • output does not change when the S, R inputs change. Therefore only when En/Cp =1 can an input be applied S Q S Q c c R Q’ R Q’ operates when operates when clock is high clock is low

  11. Clock Signals • Often, the operation of a sequential circuit is synchronized by a clock signal : • The clock signal regulates when the circuits respond to new inputs, so that operations occur in proper sequence. • Sequential circuits that are regulated by a clock signal are said to be synchronous. vC(t) positive-going edge (leading edge) negative-going edge (trailing edge) VOH time 0 TC 2TC

  12. RS Flip-Flop NOTE : and are complements of each other.

  13. Forbidden input values are forced not to occur by using an inverter between the inputs

  14. Sequential Switching Networks Reset Set Toggle Race Condition J-K Latch: Race Condition

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