EENG 449bG/CPSC 439bG Computer Systems Lecture 6 Overview of Power Issues in Computing Systems

1. EENG 449bG/CPSC 439bG Computer SystemsLecture 6 Overview of Power Issues in Computing Systems January 29, 2004 Prof. Andreas Savvides Spring 2004 http://www.eng.yale.edu/courses/eeng449bG

2. Announcements • Reading for this lecture • J. Pouwese, K. Lagendoen, H. Sips, “Dynamic Voltage Scaling on a Low Power Microprocessor”, posted on the class website • Embedded Processor Programming Reading • “Get By without an RTOS” – by Melkonian – link posted on class website • Project descriptions due tomorrow • Email: andreas.savvides@yale.edu • Microcontroller workshop tomorrow in AKW000. I recommend you attend at least 1 of these according to your project needs • 1:00 – 2:00pm ARM/THUMB programming and tools • 2:00 – 2:15pm Break • 2:15 – 3:15pm Mote programming & tools

3. Why worry about power?Intel vs. Duracell • No Moore’s Law in batteries: 2-3%/year growth 16x 14x Processor (MIPS) 12x Hard Disk (capacity) 10x Improvement(compared to year 0) 8x Memory (capacity) 6x 4x Battery (energy stored) 2x 1x 0 1 2 3 4 5 6 Time (years)

4. Current Battery Technology is Inadequate • Example: 20-watt battery • NiCd weighs 0.5 kg, lasts 1 hr, and costs $20 • Comparable Li-Ion lasts 3 hrs, but costs > 4x more

5. Comparison of Energy Sources Assume 1mW Average as definition of “Scavenged Energy”

6. Trends in Total Power Consumption source : arpa-esto • Frightening: proportional to area & frequency DEC 21164 microprocessor power dissipation

7. Power Metrics in Microprocessors nJ/Instruction • Mostly for processors with the same instruction sets • Does not capture the effect of operand size (e.g 8-bit addition vs. 32-bit addition operations MIPS/Watt mA – common among component data sheets Remember:

8. Modeling the Battery Behavior • Theoretical capacity of battery is decided by the amount of the active material in the cell • batteries often modeled as buckets of constant energy • e.g. halving the power by halving the clock frequency is assumed to double the computation time while maintaining constant computation per battery life • In reality, delivered or nominal capacity depends on how the battery is discharged • discharge rate (load current) • discharge profile and duty cycle • operating voltage and power level drained

9. Battery Capacity from [Powers95] • Current in “C” rating: load current nomralized to battery’s capacity • e.g. a discharge current of 1C for a capacity of 500 mA-hrs is 500 mA

10. Battery Capacity vs. Discharge Current • Amount of energy delivered is decreased as the current (rate at which power is drawn) is increased • rated as ampere hours or watt hours when discharged at a specific rate to a specific cut-off voltage • primary cells rated at a current which is 1/100th of the capacity in ampere hours (C/100) • secondary cells are rated at C/20 or C/10 • At high currents, the diffusion process that moves new active material from electrolytes to the electrode cannot keep up • concentration of active material at cathode drops to zero, and cell voltage goes down below cut-off • even though active material in cell is not exhausted!

11. Battery Energy Consumers

12. ARM/THUMB 40MHz Running uCos-ii RS-485 & External Power ADXL 202E MEMS Accelerometer PALOS MCU I/F Host Computer, GPS, etc UI: Pushbuttons Medusa MK-2 An Example Wireless Platform

13. Processing Programmable Ps & DSPs (apps, protocols etc.) ASICs Memory Communication RF Transceiver Radio Modem Where does the Power Go? Peripherals Disk Display Power Supply DC-DC Converter Battery

14. Power Consumption for a Computer with Wireless NIC

15. Energy Consumption ofWireless NICs (Wavelan)

16. Example: Power Consumption for Compaq’s iPAQ 206MHz StrongArm SA-1110 processor 320x240 resolution color TFT LCD Touch screen 32MB SDRAM / 16MB Flash memory USB/RS-232/IrDA connection Speaker/Microphone Lithium Polymer battery PCMCIA card expansion pack & CF card expansion pack • * Note • CPU is idle state of most of its time • Audio, IrDA, RS232 power is measured when each part is idling • Etc includes CPU, flash memory, touch screen and all other devices • Frontlight brightness was 16

17. Microprocessor Power Consumption CMOS Circuits (Used in most microprocessors) Static Component Bias and leakage currents O(1mW) Dynamic Component Digital circuit switching inside the processor Dynamic Static

18. Power Consumption in Digital CMOS Circuits - current constantly drawn from the power supply - determined by fabrication technology • short circuit current due to the DC path between the • supply rails during output transitions - load capacitance at the output node - clock frequency - power supply voltage

19. DVS on Low Power Processor Number of gates Maximum gain when voltage is lowered BUT lower voltage increases circuit delay Dynamic Power Component Load capacitance of gate k Propagation delay Transistor gain factor CMOS transistor threshold voltage

20. Voltage Scaling on LART • Dynamically lower the processor voltage and frequency to reduce power consumption • LART wearable board • StorngARM 1100 Processor 190MHz • Various I/O capabilities • 32 MB volatile memory • 4 MB non-volatile memory • Programmable voltage regulator

21. Processor Envelope

22. LART Power Measurement Based on dhrystone benchmark • Note the measurement setup at • Different levels on the board • Always provide hooks for • measurement, testing and debugging • during your design. Both for • software and hardware!!! Total Power Consumption on the LART Platform

23. Memory Subsystem Power Consumption – Read Operation Optimal memory access waveforms Power consumption Memory Bandwidth

24. Energy breakdown for read(based on 1MB read) Regulator Loss-factor

25. Power Breakdown for H.263 Decoder

26. Reducing Power Consumptionis a multilevel task! • Physical layer • Technology – reduce the surface of CMOS circuits • Architecture/IC level • Several optimizations in the design (e.g parallelism and pipelining) • Provide hooks for software driven power management (e.g different power modes and clock speeds) • OS Level • Smart schedulers, interval schedulers, DVS • Application Level • Power aware applications that worn the OS and the hardware about the features needed during application lifetime • Sleep modes and DVS driven by applications • Network Level • Networked devices may be able to apply low duty cycles, in which some of the devices are asleep and others are awake

27. Conclusions • Interval based schedulers not so efficient • Interval-scheduler – reduce voltage after a pre-specified idle period is detected • Better leverage of DVS when the processor is aware of the application requirements • Illustrated with the H.263 encoder • Monitor different power consumption profiles across different sections of the platform and use them to make clever decisions about power-management • What is missing: • Comments on power regulator efficiencies…

28. How can power consumption be reduced at the circuit design level inside a processor?

29. Critical path delay: Tadder + Tcomparator = 25 ns • Frequency: fref = 40 MHz • Total switched capacitance = Cref • Vdd = Vref = 5V • Power for reference datapath = Pref = CrefVref2fref Example: Reference Datapath from “Digital Integrated Circuits” by Rabaey

30. The clock rate can be reduced by x2 with the same throughput: fpar = fref/2 = 20 MHz • Total switched capacitance = Cpar = 2.15Cref • Vpar = Vref/1.7 • Ppar = (2.15Cref)(Vref/1.7)2(fref /2) = 0.36Pref Parallel Datapath from “Digital Integrated Circuits” by Rabaey

31. fpipe = fref Cpipe = 1.1Cref Vpipe = Vref/1.7 • Voltage can be dropped while maintaining the original throughput • Pipe = CpipeVpipe2fpipe = (1.1Cref)(Vref/1.7)2fref = 0.37Pref Pipelined Datapath from “Digital Integrated Circuits” by Rabaey

32. Datapath Architecture-Power Trade-off Summary

33. Power Consumption on Embedded Processors • Different core I/O from Peripheral I/O – numbers here • Cores scaling down to 0.8V. 1.8V devices are becoming common • General Purpose I/O interfaces still at 3.0 – 3.3V • Makes power supply harder, additional regulator inefficiency • Sleep modes and associate cost of sleep and recovery SA-1100 modes • Need time and energy to transition between states

34. Example: SA-1100 CPU 400 mW • RUN • IDLE • CPU stopped when not in use • Monitoring for interrupts • SLEEP • Shutdown on-chip activity RUN 10 ms 90 ms 10 ms 160 ms IDLE SLEEP 90 ms 50 mW 0.16 mW

35. Low-power Software • Wireless industry  Constantly evolving standards • Systems have to be flexible and adaptable • Significant portion of system functionality is implemented as software running on a programmable processor • Software drives the underlying hardware • Hence, it can significantly impact system power consumption • Significant energy savings can be obtained by clever software design.

36. Low-power Software Strategies • Code running on CPU • Code optimizations for low power • Code accessing memory objects • SW optimizations for memory • Data flowing on the buses • I/O coding for low power • Compiler controlled power management CPU Cache Memory

37. Code Optimizations for Low Power • High-level operations (e.g. C statement) can be compiled into different instruction sequences • different instructions & ordering have different power • Instruction Selection • Select a minimum-power instruction mix for executing a piece of high level code • Instruction Packing & Dual Memory Loads • Two on-chip memory banks • Dual load vs. two single loads • Almost 50% energy savings

38. Code Optimizations for Low Power (contd.) • Reorder instructions to reduce switching effect at functional units and I/O buses • E.g. Cold scheduling minimizes instruction bus transitions • Operand swapping • Swap the operands at the input of multiplier • Result is unaltered, but power changes significantly! • Other standard compiler optimizations • Intermediate level: Software pipelining, dead code elimination, redundancy elimination • Low level: Register allocation and other machine specific optimizations • Use processor-specific instruction styles • e.g. on ARM the default int type is ~ 20% more efficient than char or short as the latter result in sign or zero extension • e.g. on ARM the conditional instructions can be used instead of branches

39. Minimizing Memory Access Costs • Reduce memory access, make better use of registers • Register access consumes power << than memory access • Straightforward way: minimize number of read-write operations, e.g. • Cache optimizations • Reorder memory accesses to improve cache hit rates • Can use existing techniques for high-performance code generation

40. Minimizing Memory Access Costs (contd.) • Loop optimizations such as loop unrolling, loop fusion also reduce memory power consumption • More effective: explicitly target minimization of switching activity on I/O busses and exploiting memory hierarchy • Data allocation to minimize I/O bus transitions • e.g. mapping large arrays with known access patterns to main memory to minimize address bus transitions • works in conjunction with coding of address busses • Exploiting memory hierarchy • e.g. organizing video and DSP data to maximize the higher levels (lower power) of memory hierarchy

41. Computation & Communication Mote-class Node • Energy/bit  Energy/op large even for short ranges! WINS-class Node Energy breakdown for image Energy breakdown for acoustic Decode Decode Transmit Encode Encode Receive Receive Transmit

42. Next time • ARM/THUMB Programming & Peripherals • Embedded Operating Systems • Don’t forget tomorrow’s workshop! • 1:00pm AKW 000