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Superscalar Architecture Design Framework for DSP Operations

Superscalar Architecture Design Framework for DSP Operations. Rehan Ahmed. Overview. Optimization tool. Alters superscalar architectural configuration parameters to suit a given DSP application. It alters the architectural blocks (Number of ALU, Cache Size etc). Motivation.

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Superscalar Architecture Design Framework for DSP Operations

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  1. Superscalar Architecture Design Framework for DSP Operations Rehan Ahmed

  2. Overview • Optimization tool. Alters superscalar architectural configuration parameters to suit a given DSP application. • It alters the architectural blocks (Number of ALU, Cache Size etc).

  3. Motivation • Giving designers an initial idea about how their design should look like. • Particularly useful for software defined radio applications.

  4. Optimizations can target both power consumption and speed. • Target Function: SimplescalarWATTCH • Stage 1: Search and optimization algorithm (Simulated Annealing) • Stage 2: Heuristic Approach

  5. Simulated Annealing

  6. Simulated Annealing Parameter set

  7. Final configuration from simulated annealing further optimized using the heuristic approach • Heuristic approach based on the operating principle of superscalar architecture.

  8. Optimization Results • IFFT Operation • Scale=40 (High precedence given to efficiency)

  9. Results Summary • Optimized Configuration performance measures • Instructions per Cycle: 1.1934 • Average Power per Instruction: 4.6744 • Instructions per second (1GHz) 1.193421 G • Transistor Count 10,645,929 • Transistor Count for Pentium III 9,500,000

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