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Ultra-Deep submicron technology

Ultra-Deep submicron technology. Etienne Sicard Insa etienne.sicard@insa-tlse.fr http://intrage.insa-tlse.fr/~etienne. Summary. Ultra-deep submicron technology Specific features Embedded Memory Magnetic RAM SOI conclusion . 1. Ultra-deep submicron technology. Sub-micron.

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Ultra-Deep submicron technology

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  1. Ultra-Deep submicron technology Etienne Sicard Insa etienne.sicard@insa-tlse.fr http://intrage.insa-tlse.fr/~etienne E. Sicard - ultra deep submicron

  2. Summary • Ultra-deep submicron technology • Specific features • Embedded Memory • Magnetic RAM • SOI • conclusion E. Sicard - ultra deep submicron

  3. 1. Ultra-deep submicron technology Sub-micron Micron Nano Ultra Deep-sub micron Deep-sub micron 2.0 80286 80386 1.0 486 pentium pentium II 0.3 0.2 Pentium IV Itanium 0.1 0.05 0.03 83 86 89 92 95 98 01 04 07 Year E. Sicard - ultra deep submicron

  4. 1. Ultra-deep submicron technology • Multiple technological options to optimize performance • Faster & bigger chips • Agreements to handle tremendous costs (ST,Philips,Motorola,TSMC) E. Sicard - ultra deep submicron

  5. 2. Specific features Multiple metal layers Stacked vias Low K dielectric to reduce couplings Copper to speed up signal transport High K dielectric to reduce leakage Improved tretch isolation Multiple MOS options E. Sicard - ultra deep submicron

  6. 2. Specific features • High Speed: normal MOS • Very high speed: critical path • Low leakage: for low power • High voltage: for I/Os • Double-gate: for embedded EEPROM • RF : optimized for GHz amplifiers 3-6 MOS options E. Sicard - ultra deep submicron

  7. MRam RF 2. Specific features Ultra High Speed Low Leakage EEProm High Voltage High Speed Application-oriented MOS device Same basic mechanism New physical properties in EEPROM and MRam E. Sicard - ultra deep submicron

  8. 2. Specific features 2.5V 1.2V 1.2V 1.2V 1.2V 1.2V 2.5V High Voltage High Speed Low leakage 2.5V 1.8V Example in 0.12µm technology E. Sicard - ultra deep submicron

  9. 2. Specific features Option layer Simple access to low leakage, high voltage and isolated Pwell Option layer properties E. Sicard - ultra deep submicron

  10. 2. Specific features Low leakage High speed High voltage Simulation of the 3 MOS options E. Sicard - ultra deep submicron

  11. 2. Specific features Small Ion reduction Ioff ~100pA Ioff ~10nA Low leakage High speed Low leakage MOS has higher Vt, slight Ion reduction Low leakage MOS has 1/100 Ioff of high speed MOS E. Sicard - ultra deep submicron

  12. 2. Specific features 0.1µm process (TSMC+ST+IBM+…) Each MOS is optimized for a target customer application Towards a world-wide standard process which will ease design E. Sicard - ultra deep submicron

  13. Non volatile Volatile eDRAM SRAM ROM EEPROM FRAM 3. Embedded Memory • 80% of a system-on-chip • Bottleneck for bandwidth Cmos Embedded memories E. Sicard - ultra deep submicron

  14. CS CB 3. Embedded Memory Parasitic capacitance: 2fF Specific capacitance: 3-30fF E. Sicard - ultra deep submicron

  15. 3. Embedded Memory Double-Gate MOS 2nd Poly Floating Poly Used in EPROM, EEPROM and Flash memories E. Sicard - ultra deep submicron

  16. Ids Ids Single gate Single gate Double gate Vds Vds Gate discharged Gate charged 3. Embedded Memory Double-Gate MOS E. Sicard - ultra deep submicron

  17. 3. Embedded Memory Double-Gate MOS: write/erase by tunneling 0V 12V “Cold” electron Tunneling “Hot” electron Tunneling 0 12V Vdd Accelerate erase write Dense but slow E. Sicard - ultra deep submicron

  18. 4. Magnetic RAM Dense, fast, non-volatile: universal memory Silicium, Cobalt et Nikel 2 stage magnetic states equal to I=5mA A high magnetic field changes the state of the material E. Sicard - ultra deep submicron

  19. 4. Magnetic RAM Column i/2 i/2 Line i/2 i/2 Erase Write i/4 Principles: Write: i/2 on the line, i/2 on the column gives a current high enough to change the state Read: i/4 on the line, i/4 on the column and monitor the attenuation of current due to magnetic state i/4 Read E. Sicard - ultra deep submicron

  20. Fully or partially depleted? Kink effect 5. Silicon-On-insulator The next major evolution? CMOS compatible Less distance between nMOS and pMOS Less capacitance Less leakage >50% faster circuits E. Sicard - ultra deep submicron

  21. 6. Conclusion • The ultra-deep submicron technologies introduce new features • Low leakage MOS targeted for low power • High voltage MOS introduced for I/O interfacing • Double-poly MOS for EPROM/Flash memories • Embedded memory are key components for System-on-chip • Magnetic RAM to become the “universal memory” • SOI has many promising features, some design issues pending E. Sicard - ultra deep submicron

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