Digital Filtering

Digital Filtering

Objectives After completing this module, you will be able to: • State various filters supported in System Generator • Describe the FIR filter implementation and understand how to take advantage of certain filter parameters • Describe the integration of FDATool block in System Generator

Outline • Introduction • FIR Filters • DA Filters • MAC FIR Filters • CIC Filters • IIR Filters • Generating Coefficients • FDATool and XFLDATool • Exporting Coefficients • Simulink Tips and Tricks • Plotting Functions • Spectrum Scope • White Noise

Introduction • Digital filters are the most common of functions found in DSP systems • Following blocks are supported by System Generator for digital filtering • FIR block • CIC block • Digital filtering technique to be used will depend on several factors • Sample rate • Sample width • Coefficients profile • Clock rate

DA FIR Filter Block • Implements a single channel, single and multi-rate finite-impulse response (FIR) digital filter • In multi-channel, a single FIR filter is used in time division multiplexing mode so that the amount of resource utilization virtually remains same at the expense of reduced sample rate • The DA FIR filter provides optional ports for coefficient reloading • When a reload sequence is initiated, the filter stops accepting new data input samples and begins accepting new filter coefficients • The amount of time required for the filter to reload is a function of the filter length and type Reloading Option Fixed Option

DA FIR Filter • Supported features • Parameterizable coefficient width • Two to 1024 taps • One to eight channels • Polyphase interpolation/decimation • Optimization for symmetry, half-band, interpolated filters • Parallel, serial and multi-clock per output implementation

Twos ComplementSerial Multiply • One bit at a time:

1 Z-1 A0 00000...0 0 C0 1 LUT contains two locations SDA 1-Tap FIR Filter N BITS WIDE SAMPLE DATA Partial Product ROM A0 +/- X0 Parallel to serial converter Scaling Accumulator

Distributed Arithmeticfor a 2-Tap Filter • Partial products of equal weight are added together before being summed to next higher partial product weight • Create look-up table of summed partial products -23 22 21 20 -23 22 21 20 C0 = 1 0 0 1 (-7) C1 = 0 1 1 0 ( 6) X X0 = 0 1 1 1 ( 7) X X1 = 0 1 0 1 ( 5) + + + + ( 1 0 0 1 ( 1 0 0 1 ( 1 0 0 1 (0 0 0 0 1 1 0 0 1 1 1 1 0 1 1 0) 0 0 0 0 ) 0 1 1 0 ) 0 0 0 0 ) 0 0 0 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 0 0 0 = 1 1 1 0 1 1 0 1 (-1) (-14) (-4) (0) (-19) (-49) ( 30) (Serial-Data / Tap-Parallel Multiply) = Sign Extension

0000...0 C0 Z-1 C1 C0 + C1 1 00 01 10 11 LUT contains all possible sums of the partial products SDA 2-Tap FIR Filter N BITS WIDE SAMPLE DATA Partial Product ROM A0 X0 +/- A1 X1 Scaling Accumulator

Z-1 +/- Scaling Accumulator SDA 4-Tap FIR Filter N BITS WIDE SAMPLE DATA Partial Product ROM A0 0000...0 X0 C0 1 + A1 0000...0 X1 C1 1 + A2 0000...0 X2 C2 1 + A3 0000...0 X3 C3

1 1 1 1 1 1 1 Z-1 SDA 8-Tap FIR Filter N BITS WIDE SAMPLE DATA A0 Partial Product ROM X0 A1 X1 A2 Pre-Adder X2 A3 X3 + +/- A0 X4 Partial Product ROM Scaling Accumulator A1 X5 A2 X6 4 -input LUT contains all possible sums of the partial products A3 X7

60 Single MAC DA FIR B=8 50 DA FIR B=12 40 DA FIR B=16 Sample Rate (MSPS) 30 Serial FPGA FIR 20 10 0 0 50 100 150 200 250 Xilinx DA FIR Performance 6000 Dual MAC DA FIR B=8 5000 DA FIR B=12 4000 DA FIR B=16 3000 Performance (MMACs/s) Serial FPGA FIR 2000 1000 0 0 50 100 150 200 250 Filter Length (Taps) Filter Length (Taps) fclk = 200 MHz for both processor and FPGA B = data sample precision for FPGA

Exploiting Filter Symmetry • Impulse response often possesses symmetry • Symmetry or negative symmetry • Symmetry is exploited to produce efficient FPGA implementation • Uses half the number of multipliers, thus a large size reduction • Number of clock cycles increases by 1 due to pre-adder Z-1 Z-1 Z-1 Z-1 x ( n ) Z-1 Z-1 Z-1 Z-1 + + + + a0 a4 a1 a3 a2 ) + + + + y ( n Symmetric FIR Implementation Symmetric FIR - Odd number of coefficients

0.6 0.4 NUM. TAPS = 11 0.2 0 -0.2 0 2 4 6 8 10 COEFFICIENT INDEX y ( n ) Half-Band FIR • Odd number of coefficients (every other coefficient is zero) • Half-band implementation (for odd number of coefficients) Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 Z-1 x ( n ) a10 a8 a0 a4 a6 a2 a5 + + + + + +

Chan n - X0 Chan n - X0 Chan n - X0 ……. ……. ……. Chan 2 - X0 Chan 2 - X0 Chan 2 - X0 Chan 1 - X0 Chan 1 - X0 Chan 1 - X0 Multi-channel N-bit Sample Data X0 FIR FILTER Ch n Ch 2 Ch 1 . . . Up to 8 channels Output sample rate = FIR Sample rate # of channels C0 Out SUM Ch n Ch 2 Ch 1 . . . C1 Sample rate reduced as more channels are processed C2 K SUMs K TAPS LONG

Interpolated Filter M(zk) Image Rejection Filter I(z) y(n) x(n) Interpolated FIR Applications • Interpolated filter and image rejection filters • Interpolated FIR implementation for narrow-band filters Type ‘InterpolatedFIR’ to view the example x(n) Z-k Z-k Z-1 Z-k Z-k anm-1 a1 a3 a2 a0 + y(n) + + +

Trade Clock Cycles for Logic Area Trade Clock Cycles for Logic Area Multi bits per clock cycle 160Ms/s 20Ms/s b7 b7 b7 Serial-DA Parallel-DA b4 b3 b0 Hardware Over-sampling = 4 b0 Hardware Over-sampling = 8 Hardware Over-sampling = 2 b0 b0 b7 b3 Hardware Over-sampling = 1 b4 b0 The sample is serialized and processed 1 bit per clock cycle. 8 clock cycles are thus required to process the whole sample The sample is serialized and processed 2 bits per clock cycle. 4 clock cycles are thus required to process the whole sample The sample is processed in parallel 8 bits per clock cycle The sample is serialized and processed 4 bits per clock cycle b0

Filter Throughput • The filter sample rate is a function of: • Clock frequency, fclk • Input data sample width, B • Hardware over-sampling rate • Coefficient symmetry and number of channels • One channel, FIR filter • Over-sampling = fclk / fs • Fully serial implementation • Non symmetric: Hardware over-sampling rate = B • Symmetric: Hardware over-sampling rate = B + 1

Questions • How many clock cycles per input are required for a fully parallel 12-bit data, 20-tap symmetric filter? • The requirement for a filter is to run at 25 MSPS. A 100-MHz system clock is available on the board. What should the hardware over-sampling rate parameter be set to for 8-bit data? • How many clock cycles per input are necessary to process in serial an 11-bit data, 31-tap symmetric filter?

· Sample Memory · Cyclic RAM buffer · Depth = Taps Full Multiplier · • Sample - width × max Coeff - width Width = Sample size 8 Sample 26 26 in Samples CE + 20 92 × 8 D Q D Q Sample + Address 12 Coefficients Coefficient Capture of final result 92 × 12 N-1 Address • Simple register yn = S xn-i hi • Supports result size i=0 Accumulator • Sample - width depends on number of taps MAC Filter • The output of the filter at time n • Can be implemented using single multiply and accumulate (MAC) engine • Can also be implemented using n MACs (parallel technique), or • Using between 1 and n MACs (MAC Farm technique) • Samples can be stored in • Distributed RAM • Block RAM • SRL16E • Embedded multipliers may be considered for this architecture • No high-level block in the System Generator • There is a customizable core available • A reference design is available in Reference Blockset

MAC FIR Core • The Xilinx MAC FIR core implements a highly configurable, high-performance, and area efficient FIR filter • Single-rate polyphase decimators and interpolators are supported • Multiple data channel operation is supported for all filter types • Symmetry in the coefficient set is exploited for single MAC implementations to increase overall performance and minimize resource utilization • Data-paths provide full-precision arithmetic to avoid overflow

The Normal FIR Filter structure can be implemented using the MAC Core in a parallel technique. In this case samples stored in registers. Maybe implementation issues as number of taps increase due to adder tree Transpose FIR Structure Normal FIR Transpose FIR s(n) s(n) k0 k1 k2 k3 k3 k2 k1 k0 y(n) ‘0’ Note : Coefficient order reversed y(n) • The Transpose FIR Filter structure uses adder chain • No high level block in System Generator implemented using basic elements

1 MAC Engine Clock Rate MAC Engine Sample Rate = Multi-bit Processing Number of Taps SDA semi-parallel Clock Rate or = Clock Rate (Symmetry) ½ × Number of Taps Sample Rate = X BAAT Sample-bits (+1) Block RAM Distributed RAM External RAM Serial Processing Techniques Parallel Techniques Full Parallel FIR Sample Rate = Clock Rate Clock Rate SDA Sample Rate = Sample-bits (+1) Filter Selection Sample Rate 75 25 50 75 250 500 750 2.5 5.0 7.5 25 50 75 500 MHz 20 kHz 200 kHz 2 MHz 20 MHz 200 MHz

CIC Filter Block • Cascaded integrator-comb (CIC) filters are multi-rate filters used for realizing large sample rate changes in digital systems • Both decimation and interpolation structures are supported • CIC filters contain no multipliers; they consist only of adders, subtractors and registers • They are typically employed in applications that have a large excess sample rate; that is, the system sample rate is much larger than the bandwidth occupied by the signal • Frequently used in digital down-converters and digital up-converters

CIC Decimator • The CIC decimator consists of a cascade of integrators followed by a resampling switch and a cascade of differentiators • The integrator section consists of N ideal integrator stages operating at the high sampling rate fs • The comb section operates at a slower rate fs/R, R is the integer rate change factor • The differential delay M in the differentiator chain may be defined by the user to be either 1 or 2 • To ensure high system clock frequencies, the CIC decimator is actually implemented using the pipelined architecture

CIC Interpolator • CIC Interpolator consists of a cascade of differentiators followed by a cascade of integrators • Data is presented to the filter at the rate fs/R where it is processed by the differentiators • The rate expander causes a rate increase by a factor R by inserting R-1 zero valued samples between consecutive samples of the comb section output • The up-sampled and filtered data stream is presented to the output at the sample rate fs

CIC Block Parameters • Filter Type : Interpolator or Decimator • Sample Rate Change : 8 to 16384 (inclusive) • Number of Stages : 1 to 8 (inclusive) • Differential Delay : 1 or 2

IIR Filters • Lower order than FIR filter, i.e., less number of taps • Characterized by having infinite impulse response • Involves using previously computed values of the output signal as well as the input signal in the computation of the present output • Build using basic blocks (multipliers, registers, adders) Sin Sout  Basic algorithm assumes no additional sample delays in feedback path a1 All input related calculations have bit-widths defined by the input samples a2 b1 Feedback path must support the largest value expected and can result in large bit-widths a3 b2 A second order filter consists only of coefficients a1, a2, a3, b1, and b2 a4 b3 a5 b4

IIR Filter Example • A 2nd order IIR filter can be built using five multipliers, five registers, and an adder tree • using constant multipliers implemented in LUTs • Using embedded multipliers • Multipliers and adder tree are of full resolution, however need a quantization block at the output of the adder tree to control the output width Type ‘sysgenIIR_DFormI’ to view the example

Xilinx FDATool Block • The Xilinx FDATool (Filter Design and Analysis Tool) block provides an interface to the FDATool software available as part of the MATLAB Signal Processing Toolbox • Xilinx FDATool provides a powerful means for defining digital filters with a graphical user interface • The block will not function properly and should not be used if the Signal Processing Toolbox is not installed • This block provides a means of defining an FDATool object and storing it as part of a System Generator model • Does not use any hardware resources

FDATool Block Usage • Copy an FDATool block into a subsystem where a filter is defined • Double-clicking the icon in your Simulink model opens up an FDATool session and graphical user interface • The filter is stored in internal data structure of the FDATool block • The coefficients can be extracted using MATLAB helper functions • xlfda_numerator(‘FDATool’) returns the numerator • xlfda_denominator(‘FDATool’) to returns the denominator

FDATool Session

Effect of Quantizing

Exporting Coefficients • Once the filter is designed, coefficients can be exported using File  Export from the FDATool Block GUI • Can be exported to • Workspace (provide variable name) • Text-File (provide text file name) • M-File (provide M-file name)

Saving Coefficients • If the FIR filter block (or any other Xilinx block) is using variables from the workspace, it is desirable to load those variables (e.g., filter coefficients) from a file and have them loaded every time the file is opened • To do this, create a MATLAB .m file that contains the coefficients in a vector. An example below shows the file Load_coef.m:Coef = [-0.0043 0.0024]; • Use set_param to set the Simulink model parameter "PreLoadFcn" set_param(‘design_name’,’PreLoadFcn’,‘Load_coef’) • The PreLoadFcn will run a script to create the variable and place it in the workspace • The MATLAB path must be set to the location of the .m file for MATLAB to find the function

Saving Coefficients • Alternatively, create an M-file with coefficients defined in it • Right-click anywhere on the design sheet and select Model Properties to open a form • Enter the filename (without .m extension) in the “model pre-load function” field of the “Callbacks” tab and click OK

The Product You are DSP Designer at Cyberdyne Systems. Your company is investigating using Digital Filters instead of analog for their Security Tag detectors in an attempt to improve performance and reduce cost of the overall system. This will enable them to further penetrate the growing security market space. The specification of the single channel, single rate filter is specified below: Band Pass Filter Sampling Frequency (Fs) = 1.5 MHz Fstop 1 = 270 kHz Fpass 1 = 300 kHz Fpass 2 = 450 kHz Fstop 2 = 480 kHz Attenuation on both sides of the passband = 54dB Pass band ripple = 1 Cyberdyne has chosen to go with FPGAs due to their flexibility, time to market and performance advantages over DSP Processors. Your HDL design experience is limited and hence System Generator for DSP appears to be an excellent solution for implementing the filter in an FPGA, as you are already familiar with The MathWorks products.

Stage 1: The Prototype Your manager Miles Booth has requested that you create a prototype of the filter to be implemented on their Virtex-II Pro™ prototype board that is almost complete. The prototype must be finished as quickly as possible for the imminent Aggressive Security convention, which is the industry’s largest convention of the year so it must not be missed. Band Pass Filter Sampling Frequency (Fs) = 1.5 kHz Fstop 1 = 270 kHz Fpass 1 = 300 kHz Fpass 2 = 450 kHz Fstop 2 = 480 kHz Attenuation on both sides of the passband = 54dB Pass band ripple = 1 Data Bit Width = 8 Bits Coefficient Bit Width = 12 Bits

Lab 3: Design a FIR Filter • In this lab, you are asked to design a bandpass FIR filter • Use the FDATool to create the coefficients and pass to the FIR block • Use the DA FIR filter token to simulate and implement this filter

Basic MATLABPlotting Functions • Commonly used general and plotting functions for system generator designs: • plot(y, x) - general plotting function • stem(x) - useful for viewing an impulse response • Hold on - allows more than one plot on the same figure • Hold off - switches off hold on • Grid - displays a grid on the plot • fft(x, 1024) - performs a 1024pt FFT on data ‘x’; • abs(x) - use this to find the magnitude of number • Angle (x) - use this to find the phase of a number • Use help for further information on usage Stem plot of a Low Pass Filter’s impulse response Plot of the Magnitude Frequency response of the same Low Pass Filter

Using the Spectrum Scope • The Spectrum is extremely useful for performing a frequency analysis on your design and can be found in the DSP blockset  DSP sinks library • As no System Generator designs will use frame-based data, the input must be “buffered” (under the Scope properties). The size of the buffer determines the resolution of the FFT performed • Use overlapping to avoid the discontinuities of using finite data • Use the “Axis properties” to control the axes scale and units

Using the Spectrum Scope • The example takes two chirp signals (frequency-varying Sine Waves), adds them together and views the results on the Spectrum Scope • Note: Be aware of the window that is being used by the scope, especially when analyzing small data sets. The default is hamming and can only be changed by looking under the mask and changing the property on the window block Type ‘SpectrumScope’ to view the example

Using White Noise • An excellent block to complement the Spectrum Scope is the Gaussian White Noise block (Communications Blockset  Comms sources). This block outputs a signal over all frequencies below the Nyquist frequency • Useful to view filter cutoffs • Make sure you do not output vectors or frame-based data as System Generator designs do not accept them Type ‘WhiteNoise’ to view the example

Digital Filtering