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Active Noise Cancellation. Jessica Arbona & Christopher Brady Dr. In Soo Ahn & Dr. Yufeng Lu, Advisors. Outline . Goal Adaptive Filter Adaptive Filtering System Four Typical Applications of Adaptive Filters How does the Adaptive Filter Work? Project Description High Level Flowchart
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Active Noise Cancellation Jessica Arbona & Christopher Brady Dr. In Soo Ahn & Dr. Yufeng Lu, Advisors
Outline • Goal • Adaptive Filter • Adaptive Filtering System • Four Typical Applications of Adaptive Filters • How does the Adaptive Filter Work? • Project Description • High Level Flowchart • Equipment List • Design Approach • Procedure • MATLAB Simulation (Speech Data) • Hardware Design (Ultrasound Data) • FIR filter structures (Ultrasound Data) • DSP/FPGA Implementation (Speech Data) • Demonstration • Conclusion
Goal • The goal of the project is to design and implement an active noise cancellation system using an adaptive filter.
Adaptive Filtering System • The adaptive filtering system contains four signals: reference signal, d(n), input signal, x(n), output signal, y(n), and the error signal, e(n). The filter, w(n), adaptively adjusts its coefficients according to an optimization algorithm driven by the error signal. ∑
Four Typical Applications of Adaptive Filters ∑ ∑ Adaptive System Identification Adaptive Noise Cancellation ∑ Adaptive Prediction Adaptive Inverse
How does the Adaptive Filters Work? • Cost Function • Wiener-Hopfequation • D • Least Mean Square (LMS) • Recursive Least Square (RLS)
LMS implementation • Widrow-Hoff LMS Algorithm • d
Convergence of LMS • µ is the step size • µ must be determined in for the system to converge • f
Hardware Equipment Lists • Design Tools • MATLAB/Simulink • Xilinx System Generator • XtremeDSP development kit: • FPGA device (Virtex4 xC4SX35-10FF668) • Two 14- bit DAC onboard channels • Ultrasound Data • SignalWaveDSP/FPGA board • Audio CODEC (sampling frequency varies from 8kHZ to 48kHZ) • Real-time workshop and Xilinx system generator in MATLAB/Simulink • TI DSP (TMS320C6713) and Xilink Virtex II FPGA (XC2V300- FF1152) • Speech Data
Design Approach • Simulation • MATLAB • Least Mean Square (LMS) • Recursive Least Square (RLS) • Hardware • Least Mean Square • Design • Test FIR filter structures • Implement
Design Description • Speech Data Processing • MATLAB simulation with Tap (L) = 10 • LMS • RLS • Speech Data • Recorded Voice Signal • Recorded Engine Noise
Noise and Desired Signals Figure 1: Desired Signal Figure 3: Reference Signal Figure 2: Noise Signal
RLS & LMS Filters : Coefficients • LMS • RLS Figure 4: LMS Filter Coefficients Figure 5: RLS Filter Coefficients
Desired and Recovered Signals: L = 10 • LMS • RLS Figure 8: Desired Signal and Recovered Signal Figure 9: Desired Signal and Recovered Signal • Green – Desired Signal • Blue – Recovered Signal
Adaptive Filter Design Description: • L = 6 • Adaptive FIR Filter
Desired and Recovered Signals: L = 10 • XtremeDSP- Virtex 4 • Hardware Results Orange – Input signal Blue – Output Signal
Overall Design of the Adaptive Filter Description: • L =10 • Adaptive FIR Filter
Desired and Recovered Signals Figure 12: Desired Signal and Recovered Signal Figure 13: Spectrum of Desired and Recovered Signals
Conclusion • The adaptive filter is successfully simulated in MATLAB using various types of noise. The simulation results show a 24 dB reduction in the mean square error. These results are used in developing the Xilinx model of the system. After the system is successfully designed, alternative FIR structures are investigated in an attempt to improve efficiency. The standard FIR structure is found to be better suited for hardware implementation on a DSP/FPGA board.
Reference • The adaptive filter is successfully simulated in MATLAB using various types of noise. The simulation results show a 24 dB reduction in the mean square error. These results are used in developing the Xilinx model of the system. After the system is successfully designed, alternative FIR structures are investigated in an attempt to improve efficiency. The standard FIR structure is found to be better suited for hardware implementation on a DSP/FPGA board.