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C ENG 311

C ENG 311. MIPS INTRODUCTION. Instruction Set Architecture. Application. Software. Operating. System. Interface Between HW and SW. Compiler. Firmware. Instruction Set Architecture, Memory, I/O. CPU. I/O system. Memory. Digital Design. Circuit Design. Hardware.

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C ENG 311

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  1. CENG 311 MIPS INTRODUCTION

  2. Instruction Set Architecture Application Software Operating System Interface Between HW and SW Compiler Firmware Instruction Set Architecture, Memory, I/O CPU I/O system Memory Digital Design Circuit Design Hardware

  3. Levels of Representation temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) High Level Language Program Compiler Assembly Language Program Assembler 0000 1001 1100 0110 1010 1111 0101 1000 1010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111 Machine Language Program Machine Interpretation Control Signal Specification

  4. SOFTWARE Computer Architecture? . . . the attributes of a [computing] system as seen by the programmer, i.e. the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation. Amdahl, Blaaw, and Brooks, 1964

  5. Requirements for ISA What primitive operations do we need? (i.e., What should be implemented in hardware?) #include <iostream.h> main() { int *a = new int[100]; int *p = a; int k; for (k = 0; k < 100; k++) { *p = k; p++; } cout << "entry 3 = " << a[3] << endl; }

  6. Design Space of ISA • Five Primary Dimensions • Operations add, sub, mul, . . . • How is it specified? • Number of explicit operands ( 0, 1, 2, 3 ) • Operand Storage Where besides memory? • Memory Address How is memory location specified? • Type & Size of Operands byte, int, float, vector, . . . • How is it specified? • Other Aspects • Successor instruction How is it specified? • Conditions How are they determined? • Encoding Fixed or variable? Wide? • Parallelism

  7. Basic ISA Classes Accumulator: 1 address add A acc ¬ acc + mem[A] 1+x address addx A acc ¬ acc + mem[A + x] Stack: 0 address add tos ¬ tos + next (JAVA VM) General Purpose Register: 2 address add A B A ¬ A + B 3 address add A B C A ¬ B + C Load/Store: 3 address add Ra Rb Rc Ra ¬ Rb + Rc load Ra Rb Ra ¬ mem[Rb] store Ra Rb mem[Rb] ¬ Ra

  8. 4 3 2 Accumulator • Instruction set: Accumulator is implicit operand one explicit operand add, sub, mult, div, . . . clear Example:a*b - (a+c*b) clear 0 add c 2 mult b 6 add a 10 st tmp 10 clear 0 add a 4 mult b 12 sub tmp 2 9 instructions a b time c tmp

  9. Stack Machines • Instruction set: add, sub, mult, div . . . Top of stack (TOS) and TOS+1 are implicit push A, pop A TOS is implicit operand, one explicit operand Example:a*b - (a+c*b) push a push b mult push a push c push b mult add sub 9 instructions time C - + * C*B B A B + * A A*B A A*B A*B A C A A*B A A*B A*B - * + * a a b c b

  10. 2-address ISA • Instruction set: Two explicit operands, one implicit add, sub, mult, div, … one source operand is also destination add a,b a <- a + b Example:a*b - (a+c*b) tmp1,tmp2 add tmp1, b 3, ? mult tmp1, c 6, ? add tmp1, a 10, ? add tmp2, b 10, 3 mult tmp2, a 10, 12 sub tmp2, tmp1 10, 2 6 instructions a 4 b 3 c 2 tmp1 tmp2

  11. 3-address ISA • Instruction set: Three explicit operands, ZERO implicit add, sub, mult, div, … add a,b,c a <- b + c Example:a*b - (a+c*b) tmp1,tmp2 mult tmp1, b, c 6, ? add tmp1, tmp1, a 10, ? mult tmp2, a, b 10, 12 sub tmp2, tmp2, tmp1 10, 2 4 instructions a 4 b 3 c 2 tmp1 tmp2

  12. r0 r31 Adding Registers to an ISA • A place to hold values that can be named within the instruction • Like memory, but much smaller • 32-128 locations • How many bits to specify a register? Byte Address Data 0 00110110 1 00001100 2 3 4 • • • 2n-1-4 2n-1

  13. 3-address General Purpose Register ISA • Instruction set: Three explicit operands, ZERO implicit add, sub, mult, div, … add a,b,c a <- b + c Example:a*b - (a+c*b) r1,r2 mult r1, b, c 6, ? add r1, r1, a 10, ? mult r2, a, b 10, 12 sub r2, r2, r1 10, 2 4 instructions a 4 b 3 c 2

  14. LOAD / STORE ISA • Instruction set: add, sub, mult, div, … only on operands in registers ld, st, to move data from and to memory, only way to access memory Example: a*b - (a+c*b) r1,r2,r3 ld r1, c 2, ?, ? ld r2, b 2, 3, ? mult r1, r1, r2 6, 3,? ld r3, a 6, 3, 4 add r1, r1, r3 10, 3, 4 mult r2, r2, r3 10,12, 4 sub r3, r2, r1 10, 12, 2 7 instructions a 4 b 3 c 2

  15. ... x 0x26cf0 p 0x26d00 0x26cbf0 Using Registers to Access Memory • Registers can hold memory addresses Given int x; int *p; p = &x; *p = *p + 8; Instructions ld r1, p // r1 <- p ld r2, 0(r1) // r2 <- mem[r1] add r2, r2, 0x8 // increment x by 8 st r2, 0(r1) // mem[r1] <- r2 • Many different ways to address operands • not all Instruction sets include all modes

  16. Making Instructions Machine Readable • So far, still too abstract • add r1, r2, r3 • Need to specify instructions in machine readable form • Bunch of Bits • Instructions are bits with well defined fields • Like a floating point number has different fields • Instruction Format • Establishes a mapping from “instruction” to binary values • Which bit positions correspond to which parts of the instruction (operation, operands, etc.)

  17. A "Typical" RISC • 32-bit fixed format instruction (3 formats) • 32 64-bit GPR (R0 contains zero) • 3-address, reg-reg arithmetic instruction • Single address mode for load/store: base + displacement • no indirection see: SPARC, MIPS, MC88100, AMD2900, i960, i860 PARISC, PowerPC, DEC Alpha, Clipper, CDC 6600, CDC 7600, Cray-1, Cray-2, Cray-3

  18. Example: MIPS Register-Register 6 5 11 10 31 26 25 21 20 16 15 0 Op Rs1 Rs2 Rd Opx Register-Immediate 31 26 25 21 20 16 15 0 immediate Op Rs1 Rd Branch 31 26 25 21 20 16 15 0 immediate Op Rs1 Rs2/Opx Jump / Call 31 26 25 0 target Op

  19. A Program 2n-1 #include <iostream.h> main() { int *a = new int[100]; int *p = a; int k; for (k = 0; k < 100; k++) { *p = k; p++; } cout << "entry 3 = " << a[3] << endl; } Stack .cc file bits Data Text add r,s1,s2 0 Reserved

  20. Stored Program Computer • Instructions: a fixed set of built-in operations • Instructions and data are stored in the (same) computer memory • Fetch Execute Cycle while (true){ fetch instruction execute instruction }

  21. What Must be Specified? • Instruction Format • how do we tell what operation to perform? • Location of operands and result • where other than memory? • how many explicit operands? • how are memory operands located? • which can or cannot be in memory? • Data type and Size • Operations • what are supported • Successor instruction • jumps, conditions, branches • fetch-decode-execute is implicit! Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction

  22. MIPS ISA Categories • Arithmetic • add, sub, mul, etc • Logical • and, or, shift • Data Transfer • load, store • MIPS is LOAD/STORE architecture • Conditional Branch • implement if, for, while… statements • Unconditional Jump • support function calls (procedure or methods calls)

  23. MIPS Instruction Set Architecture • 3-Address Load Store Architecture. • Register and Immediate addressing modes for operations. • Immediate and Displacement addressing for Loads and Stores. • Examples: add $1, $2, $3 # $1 = $2 + $3 addi $1, $1, 4 # $1 = $1 + 4 lw $1, 100 ($2) # $1 = Memory[$2 + 100] sw $1, 100 ($2) # Memory[$2 + 100] = $1 lui $1, 100 # $1 = 100 << 16 addi $1, $3, 100 # $1 = $3 + 100

  24. Registers: fast memory, Integral part of the CPU. Programmable storage 232 bytes 31 x 32-bit GPRs (R0 = 0) 32 x 32-bit FP regs (paired DP) 32-bit HI, LO, PC MIPS Integer Registers

  25. 6 5 11 10 31 26 25 21 20 16 15 0 shamt Op Rs Rt Rd func MIPS Instruction Formats R-type: Register-Register I-type: Register-Immediate 31 26 25 21 20 16 15 0 immediate Op Rs Rt J-type: Jump / Call 31 26 25 0 target Op Terminology Op = opcode Rs, Rt, Rd = register specifier

  26. 31 26 25 21 20 16 15 11 10 6 5 0 Op 000000 Rs 00010 00011 Rt 00001 Rd shmt 00000 100000 func op a 6-bit operation code. rs a 5-bit source register. rt a 5-bit target (source) register. rd a 5-bit destination register. shmt a 5-bit shift amount. func a 6-bit function field. op rs rt rd shmt func R Type: <OP> rd, rs, rt Operand Addressing: Register direct Example: ADD $1, $2, $3 # $1 = $2 + $3

  27. op rs rt immediate 001000 00010 00001 1111 1111 1001 1100 I-Type <op> rt, rs, immediate 31 26 25 21 20 16 15 0 Immediate: 16 bit value Operand Addressing: Register Direct and Immediate Op Rs Rt Immediate Add Immediate Example addi $1, $2, -100# $1 = $2 + (-100) Rt becomes the destination register!

  28. 31 26 25 21 20 16 15 0 Op Rs Rt Immediate Memory Register + Register op rs rt immediate 010011 00010 00001 0000 0000 0110 0100 I-Type <op> rt, rs, immediate Load Word Example lw $1, 100($2) # $1 = Mem[$2+100] Base+index

  29. Successor Instruction main() { int x,y,same; // $0 == 0 always x = 43; // addi $1, $0, 43 y = 2; // addi $2, $0, 2 same = 0; // addi $3, $0, 0 if (x == y) same = 1; // execute only if x == y // addi $3, $0, 1 } Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction

  30. The Program Counter • Special register (pc) that points to instructions • Contains memory address (like a pointer) • Instruction fetch is • inst = mem[pc] • To fetch next sequential instruction pc = pc + ? • Size of instruction?

  31. 0x10000 0x10000 0x10004 0x10004 0x10008 0x10008 0x1000c 0x1000c The Program Counter x = 43; // addi $1, $0, 43 y = 2; // addi $2, $0, 2 same = 0; // addi $3, $0, 0 if (x == y) same = 1; // addi $3, $0, 1execute if x == y PC addi $1, $0, 43 addi $2, $0, 2 addi $3, $0, 0 addi $3, $0, 1 Clearly, this is not correct We cannot always execute both 0x10008 and 0x1000c

  32. op rs rt immediate 000101 00001 00010 0000 0000 0110 0100 I-Type <op> rt, rs, immediate 31 26 25 21 20 16 15 0 • PC relative addressing Branch Not Equal Example bne $1, $2, 100 # If ($1!= $2) goto [PC+4+100] • +4 because by default we increment for sequential • more detailed discussion later in semester Op Rs Rt Immediate Memory PC + + 4

  33. The Program Counter x = 43; // addi $1, $0, 43 y = 2; // addi $2, $0, 2 if (x == y) same = 1; // addi $3, $0, $1execute if x == y PC 0x10000 addi $1, $0, 43 0x10000 0x10004 addi $2, $0, 2 0x10004 0x10008 addi $3, $0, 0 0x10008 0x1000c bne $1, $2, 4 0x1000c 0x10010 0x10010 addi $3, $0, 1 Understand branches

  34. Successor Instruction int equal(int a1, int a2) { int tsame; tsame = 0; if (a1 == a2) tsame = 1; // only if a1 == a2 return(tsame); } main() { int x,y,same; // r0 == 0 always x = 43; // addi $1, $0, 43 y = 2; // addi $2, $0, 2 same = equal(x,y); // need to call function // other computation } Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction

  35. Branches are limited to 16 bit immediate Big programs? x = 43; // addi $1, $0, 43 y = 2; // addi $2, $0, 2 same = equal(x,y); The Program Counter 0x10000 addi $1, $0, 43 0x10004 addi $2, $0, 2 0x10008 “go execute equal” 0x30408 addi $3, $0, 0 0x3040c beq $1, $2, 8 0x30410 addi $3, $0, 1 “return $3”

  36. Jump and Link Example jal 0x0fab8# PC<- 0x0fab8, $31<-PC+4 $31 set as side effect, used for returning, implicit operand opTarget 000011 00 0000 0000 0011 1110 1010 1110 J-Type: <op> target 31 26 Op Target Address PC $31 4 + Please note, The address is a WORD ADDRESS!

  37. 31 26 25 21 20 16 15 11 10 6 5 0 000000 Op Rs 11111 Rt 00000 00000 Rd 00000 shamt 001000 func op rs rt rd shmt func R Type: <OP> rd, rs, rt Jump Register Example jr $31# PC <- $31

  38. int equal(int a1, int a2) { int tsame; tsame = 0; if (a1 == a2) tsame = 1; return(tsame); } main() { int x,y,same; x = 43; y = 2; same = equal(x,y); // other computation } 0x10000 addi $1, $0, 43 0x10004 addi $2, $0, 2 0x10008 jal 0x30408 0x1000c ?? 0x30408 addi $3, $0, 0 0x3040c bne $1, $2, 4 0x30410 addi $3, $0, 1 0x30414 jr $31 Instructions for Procedure Call and Return PC$31 0x10000 ?? 0x10004 ?? 0x10008 ?? 0x30408 0x1000c 0x3040c 0x1000c 0x30410 0x1000c 0x30414 0x1000c 0x1000c 0x1000c

  39. MIPS Arithmetic Instructions InstructionExampleMeaningComments add add $1,$2,$3 $1 = $2 + $3 3 operands subtract sub $1,$2,$3 $1 = $2 – $3 3 operands add immediate addi $1,$2,100 $1 = $2 + 100 + constant add unsigned addu $1,$2,$3 $1 = $2 + $3 3 operands subtract unsigned subu $1,$2,$3 $1 = $2 – $3 3 operands add imm. unsign. addiu $1,$2,100 $1 = $2 + 100 + constant multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product multiply unsignedmultu $2, $3 Hi, Lo = $2 x $3 64-bit unsigned product divide div $2,$3 Lo = $2 ÷ $3, Lo = quotient, Hi = $2 mod $3 Hi = remainder divide unsigned divu $2,$3 Lo = $2 ÷ $3, Unsigned quotient Hi = $2 mod $3 Unsigned remainder Move from Hi mfhi $1 $1 = Hi Used to get copy of Hi Move from Lo mflo $1 $1 = Lo Used to get copy of Lo Which add for address arithmetic? Which for integers?

  40. MIPS Logical Instructions InstructionExampleMeaningComment and and $1,$2,$3 $1 = $2 & $3 Bitwise AND or or $1,$2,$3 $1 = $2 | $3 Bitwise OR xor xor $1,$2,$3 $1 = $2 $3 Bitwise XOR nor nor $1,$2,$3 $1 = ~($2 | $3) Bitwise NOR and immediate andi $1,$2,10 $1 = $2 & 10 Bitwise AND reg, const or immediate ori $1,$2,10 $1 = $2 | 10 Bitwise OR reg, const xor immediate xori $1, $2,10 $1 = ~$2 &~10 Bitwise XOR reg, const shift left logical sll $1,$2,10 $1 = $2 << 10 Shift left by constant shift right logical srl $1,$2,10 $1 = $2 >> 10 Shift right by constant shift right arithm. sra $1,$2,10 $1 = $2 >> 10 Shift right (sign extend) shift left logical sllv $1,$2,$3 $1 = $2 << $3 Shift left by var shift right logical srlv $1,$2, $3 $1 = $2 >> $3 Shift right by var shift right arithm. srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by var

  41. LUI R5 R5 0000 … 0000 MIPS Data Transfer Instructions InstructionComment SW R3, 500(R4) Store word SH R3, 502(R2) Store half SB R2, 41(R3) Store byte LW R1, 30(R2) Load word LH R1, 40(R3) Load half word LHU R1, 40(R3) Load half word unsigned LB R1, 40(R3) Load byte LBU R1, 40(R3) Load byte unsigned LUI R1, 40 Load Upper Immediate (16 bits shifted left by 16) Why do we need LUI?

  42. MIPS Compare and Branch Compare and Branch beq rs, rt, offsetif R[rs] == R[rt] thenPC-relative branch bne rs, rt, offset<> Compare to zero and Branch blez rs, offsetif R[rs] <= 0 then PC-relative branch bgtz rs, offset> bltz rs, offset< bgez rs, offset>= bltzal rs, offsetif R[rs] < 0 then branch and link (into R 31) bgeal rs, offset>= • Remaining set of compare and branch take two instructions • Almost all comparisons are against zero!

  43. MIPS jump, branch, compare instructions InstructionExample Meaning branch on equal beq $1,$2,100if ($1 == $2) go to PC+4+100 Equal test; PC relative branch branch on not eq. bne $1,$2,100if ($1!= $2) go to PC+4+100 Not equal test; PC relative set on less than slt $1,$2,$3if ($2 < $3) $1=1; else $1=0 Compare less than; 2’s comp. set less than imm. slti $1,$2,100if ($2 < 100) $1=1; else $1=0 Compare < constant; 2’s comp. set less than uns. sltu $1,$2,$3if ($2 < $3) $1=1; else $1=0 Compare less than; natural numbers set l. t. imm. uns. sltiu $1,$2,100if ($2 < 100) $1=1; else $1=0 Compare < constant; natural numbers jump j 10000go to 10000 Jump to target address jump register jr $31go to $31 For switch, procedure return jump and link jal 10000$31 = PC + 4; go to 10000 For procedure call

  44. Signed v.s Unsigned Comparison R1= 0…00 0000 0000 0000 0001 R2= 0…00 0000 0000 0000 0010 R3= 1…11 1111 1111 1111 1111 • After executing these instructions: slt r4,r2,r1 slt r5,r3,r1 sltu r6,r2,r1 sltu r7,r3,r1 • What are values of registers r4 - r7? Why? r4 = ; r5 = ; r6 = ; r7 = ;

  45. Multiply / Divide Start multiply, divide mult rs, rt mthi rdMove to HI or LO mtlo rd Why not Third field for destination?(Hint: how many clock cycles for multiply or divide vs. add?)

  46. Summary • MIPS has 5 categories of instructions • Arithmetic, Logical, Data Transfer, Conditional Branch, Unconditional Jump • 3 Instruction Formats: R-type, I-type, J-type. Next Time • Assembly Programming Reading • Ch. 3, Appendix A

  47. An Example MIPS Program # Program #1 : (descriptive name) Programmer: YOUR NAME # Due Date : Sep. 13, 2002 Course: CS231 # Last Modified: Sep. 12, 2002 Section: 2 ######################################################### # Functional Description: Find the sum of the integers from 1 to N where # N is a value input from the keyboard. ######################################################### # Algorithmic Description in Pseudocode: # main: v0 << value read from the keyboard (syscall 4) # if (v0 < = 0 ) stop # t0 = 0; # t0 is used to accumulate the sum # While (v0 >= 0) { t0 = t0 + v0; v0 = v0 - 1} # Output to monitor syscall(1) << t0; goto main ########################################################## # Register Usage: $t0 is used to accumulate the sum # $v0 the loop counter, counts down to zero ##########################################################

  48. .dataprompt: .asciiz "\n\n Please Input a value for N = "result: .asciiz " The sum of the integers from 1 to N is "bye: .asciiz "\n **** Have a good day **** " .globl main .textmain: li $v0, 4 # system call code for print_str la $a0, prompt # load address of prompt into a0 syscall # print the prompt message li $v0, 5 # system call code for read_int syscall # reads a value of N into v0 blez $v0, done # if ( v0 < = 0 ) go to done li $t0, 0 # clear $t0 to zero loop: add $t0, $t0, $v0 # sum of integers in register $t0 addi $v0, $v0, -1 # summing in reverse order bnez $v0, loop # branch to loop if $v0 is != zero li $v0, 4 # system call code for print_str la $a0, result # load address of message into $a0 syscall # print the string li $v0, 1 # system call code for print_int move $a0, $t0 # a0 = $t0 syscall # prints the value in register $a0 b main

  49. done: li $v0, 4 # system call code for print_str la $a0, bye # load address of msg. into $a0 syscall # print the string li $v0, 10 # terminate program syscall # return control to systemMUST HAVE A BLANK LINE AT THE END OF THE TEXT FILE

  50. Yet Another Example Write a program that will compute the sum of the even positive values, minus the odd negative values in an array of words. Stop when a value of zero is found in the array. For Example: array: .word -29, -30, 75, 34, -2, 90, -11, 98, 1, 0, 76 Pseudo Code for the Algorithm: $a1 = &array; $a0 = 0; loop: $t0= Mem($a1); if ($t0 == 0) go to done $a1 = $a1 + 4; $t3 = $t0 & 1; if ($t0 >= 0 & $t3 == 0) $a0 = $a0 + $t0; else if ($t0 < 0 & $t3 != 0) $a0= $a0 - $t0; go to loop done: syscall(1) << $a0; exit

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