PIC16F877 ISR Points to note

1. PIC16F877 ISR Points to note • Interrupt Triggers • Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit, PEIE bit, or GIE bit. • When bit GIE is enabled, and an interrupt’s flag bit and mask bit are set, the interrupt will vector immediately. • Interrupt Process • When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. • Once in the Interrupt Service Routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. • The interrupt flag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts. • The “return from interrupt” instruction, RETFIE, exits the interrupt routine, as well as sets the GIE bit, which re-enables interrupts.

2. PIC16F877 ISR Points to note • Register Save/Restore • During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save key registers during an interrupt, (i.e., W register and STATUS register). This will have to be implemented in software. • Since the upper 16 bytes of each bank are common in the PIC16F876/877 devices, temporary holding registers e.g. W_TEMP, should be placed in here. These 16 locations don’t require banking and therefore, make it easier for context save and restore when the program and ISR are in different banks. • Interrupt latency • time from the interrupt event (the interrupt flag bit gets set) to the time that the instruction at the interrupt vector starts execution. • Synchronous interrupts (typically internal), the latency is 3TCY (instruction cycles).. • Asynchronous interrupts (typically external), the will be 3 - 3.75TCY The exact latency depends upon when the interrupt event occurs in relation to the instruction cycle. • Latency is the same for both one and two cycle instructions (by design).

3. Interrupt Latency

4. Interrupt sample code (1) ISR movwf w_temp ; save W and STATUS movf STATUS,W ; movwf status_temp ; Poll btfsc INTCON,TOIF ; test if TMR0 overflow occurred call Timer_hndlr ; call handler for TMR0 btfsc INTCON,INTF ; test if external interrupt occurred call Extern_hndlr ; call handler for external interrupt btfsc INTCON,RBIF ; test if PORTB change interrupt occurred call Change_hndlr ; ...etc movf status_temp,W ; restore pre-isr STATUS register movwf STATUS ; swapf w_temp,F ; restore pre-isr W register contents swapf w_temp,W ; ... without affecting the zero flag retfie ; return from interrupt Timer_hndler bcf INTCON,TOIF ; clear the overflow flag ; do processing return Extern_hndlr ; clear appropriate flag etc return Change_hndlr ; clear appropriate flag etc return

5. Interrupt sample code (2) ISR movwf w_temp ; save W and STATUS movf STATUS,W ; movwf status_temp ; Poll btfsc INTCON,TOIF ; test if TMR0 overflow occurred goto Timer_hndlr ; call handler for TMR0 btfsc INTCON,INTF ; test if external interrupt occurred goto Extern_hndlr ; call handler for external interrupt btfsc INTCON,RBIF ; test if PORTB change interrupt occurred goto Change_hndlr ; ...etc movf status_temp,W ; restore pre-isr STATUS register movwf STATUS ; swapf w_temp,F ; restore pre-isr W register contents swapf w_temp,W ; ... without affecting the zero flag retfie ; return from interrupt Timer_hndler bcf INTCON,TOIF ; clear the overflow flag ; do processing goto Poll Extern_hndlr ; clear appropriate flag etc goto Poll Change_hndlr ; clear appropriate flag etc goto Poll

6. Multiple Interrupts • On = 12 + 2N (14+2N) • the overhead time for an N interrupt source ISR • Pi = 6 + 2i (8 +2i) • from the start of the ISR • to the test of the ith interrupt source (presuming no other interrupt) • Ti -- time for the ith handler • How long: • will “Main” be “asleep”? • between event flag and ISR end? • Analysis considers all possible arrival patterns • Consider worst-cases: • ISR(1) - high priority interrupt arrives long after low priority interrupt (84; 76) • ISR(1) - high priority interrupt arrives after low priority interrupt; but before even lower priority interrupt (118;116;108) • ISR(2) - (78; 109; 117)

7. Race Conditions • who gets there first? • final result depends on the order of events • Occurs when • two separate routines (main, ISR) actively access the same variables AND/OR • successive commands must be executed without interruption Critical Sections • the code in a critical section is never interrupted • implemented on the PIC16F877 by disabling/re-enabling GIE • test for GIE after it is disabled • can be used to avoid race conditions

8. http://class.et.byu.edu/eet548/encoders.pdf Rotary Optical Encoder(Pulse Generator) http://www.controleng.com/archives/2000/ctl0701.00/0007bb.htm http://www.controleng.com/archives/2000/ctl0701.00/0007bbw1.htm B A A B

9. RPG Tie A to RB0 Tie B to another pin (RB1) Use interrupt on A rising edge ISR will check value of B to determine direction check time since last interrupt to estimate speed Frequency Measurement Tie 1s CLK to RB0 Tie frequency signal to the timer/counter external input Use interrupt on CLK rising edge ISR will store the recorded # of transitions in 1s (frequency) clear the counter Application The ISR is executed frequently, so keep as much processing in “Main” as possible.