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DM642 IBIS Issue Tech : SR40

DM642 IBIS Issue Tech : SR40. Created on Sep 13 2010. ________________________________ From: TI E2E Community - Automated Email [ mailto:noreply@e2e.ti.com ] Sent: Sunday, June 20, 2010 2:56 AM To: Gangireddy, Srirami

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DM642 IBIS Issue Tech : SR40

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  1. DM642 IBIS IssueTech : SR40 Created on Sep 13 2010

  2. ________________________________ From: TI E2E Community - Automated Email [mailto:noreply@e2e.ti.com] Sent: Sunday, June 20, 2010 2:56 AM To: Gangireddy, Srirami Subject: DM64x DaVinci Video Processor Forum: TMS320DM642 EMIF related ibis simulation on Hyper Lynx, Strange non-monotonic rising/falling edge on data pins !!!! Mohammad Bilal replied to TMS320DM642 EMIF related ibis simulation on Hyper Lynx, Strange non-monotonic rising/falling edge on data pins !!!!<http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/99/p/52900/187305.aspx#187305> in DM64x DaVinci Video Processor Forum. Hi, I have a question about TMS320DM642 EMIF related ibis simulation. Previously I designed a DSP board with TMS320C6713 and all of its simulations with SDRAM went perfectly ok. However when I performed the ibis simulation for a newer board, using TMS320DM642 EMIF with Micron Technology MT48LC4M32B2 SDRAM, I get some non-monotonic rise and fall waveform over the data pins (AED00 for example), similar to double clocking or dual edge, and it laps for about 450 ps. However the same simulation on Address and Clock Signals on DM642 is all fine. The same simulation with C6713 was all ok, no non-monitonic behaviour, as u can see in the snapshot. I wanted to ask is it all fine with the DM642-SDRAM interface ? , since I used a very simple transmission line model of 75 Ohms for it, using hyper lynx and the ti, and micron technnology provided ibis models. Here are the snapshot of simulations. Snapshot of DM642 related simulation ... [http://e2e.ti.com/resized-image.ashx/__size/550x0/__key/CommunityServer.Discussions.Components.Files/99/8831.dm642_5F00_sdram_5F00_sim.JPG]<http://e2e.ti.com/cfs-file.ashx/__key/CommunityServer.Discussions.Components.Files/99/8831.dm642_5F00_sdram_5F00_sim.JPG> And here is the C6713 related, over the same data bus, but all fine here ... [http://e2e.ti.com/resized-image.ashx/__size/550x0/__key/CommunityServer.Discussions.Components.Files/99/0143.c6713_5F00_sdram_5F00_sim.JPG]<http://e2e.ti.com/cfs-file.ashx/__key/CommunityServer.Discussions.Components.Files/99/0143.c6713_5F00_sdram_5F00_sim.JPG> I will be very thankful for the help, thanking u in advance ! ... Problem Statement

  3. Customer simulation setup/result

  4. We expect a attenuation in this curve due to resistor which is not seen (yellow)

  5. DM642 Model Pin mapping section AED00 -> maps to BT3315DTPU IO Transcript of DM642 Model is as below : Model is located at DM642 [IBIS Ver] 3.2 [File Name] sprm111.ibs [File Rev] 0.1 [Date] March 18, 2003 [Source] IBIS Model Generated from PACED 4.51F |************************************************************************** | [Component] DM642_GDK [Manufacturer] Texas Instruments [Package] |Variable Typ Min Max R_pkg 0.12581866 0.0708 0.1927 L_pkg 2.32E-09 1.26E-09 3.57E-09 C_pkg 1.14E-12 6.40E-13 1.77E-12 | [Pin] signal_name model_name R_pin L_pin C_pin C1 PCLK BPCI66T 0.1647 2.94E-09 1.24E-12 B4 NMI IT33THYPD 0.1574 2.92E-09 1.37E-12 A4 TINP0 IT33THYPD 0.1714 3.17E-09 1.50E-12 C5 TOUT0 BT3325CTPD 0.1355 2.49E-09 1.22E-12 B5 TOUT1 BT3325CTPU 0.1504 2.77E-09 1.35E-12 A5 TINP1 IT33THYPD 0.1652 3.05E-09 1.47E-12 D6 CLKOUT4 BT3315DTHYPU 0.1173 2.16E-09 1.06E-12 C6 CLKOUT6 BT3315DTHYPU 0.1352 2.50E-09 1.19E-12 C7 VP2CTL2 BT3325CTHYPD 0.1341 2.47E-09 1.19E-12 D7 VP2CTL1 BT3325CTHYPD 0.1127 2.08E-09 1.01E-12 A7 VP2CLK0 IT33THYPD 0.1549 2.87E-09 1.36E-12 D8 VP2D01 BT3325CTHYPD 0.102 1.88E-09 9.12E-13 C8 VP2D00 BT3325CTHYPD 0.1197 2.20E-09 1.07E-12 B8 VP2CTL0 BT3325CTHYPD 0.1345 2.46E-09 1.21E-12 D9 VP2D05 BT3325CTHYPD 0.0977 1.77E-09 9.19E-13 C9 VP2D04 BT3325CTHYPD 0.114 2.07E-09 1.05E-12 B9 VP2D03 BT3325CTHYPD 0.1288 2.34E-09 1.18E-12 A9 VP2D02 BT3325CTHYPD 0.1437 2.63E-09 1.29E-12 D10 VP2D09 BT3325CTHYPD 0.0946 1.70E-09 9.01E-13 C10 VP2D08 BT3325CTHYPD 0.1127 2.05E-09 1.04E-12 B10 VP2D07 BT3325CTHYPD 0.1278 2.33E-09 1.18E-12 A10 VP2D06 BT3325CTHYPD 0.143 2.62E-09 1.29E-12 |

  6. AED00:BT3315DTPU IO IBIS simulation setup in ICX Pro 75ohms Z=75, Td=30pS Z=75, Td=30pS B A DM642 XSP_DI pin IT33TPU DM642 AED00 pin BT3315DTPU IO

  7. AED00:BT3315DTPU IO IBIS simulation result 100MEG Operation, Strong corner A(green) B(yellow)

  8. AED00:BT3315DTPU IO IBIS simulation result 200MEG Operation, Strong corner A(green) B(yellow)

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