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T. ABLE. C.1. Address field encoding for 68000. Address. field. Mo. de. Register. 5. 4. 3. 2. 1. 0. Mo de. Addressing. mo de. field. Register. field. Data. register. direct. 000. Register. n. um. b. er. Address. register. direct. 001. Register. n. um. b. er.

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  1. T ABLE C.1 Address field encoding for 68000 Address field Mo de Register 5 4 3 2 1 0 Mode Addressing mode field Register field Data register direct 000 Register n um b er Address register direct 001 Register n um b er Address register indirect 010 Register n um b er Autoincrement 011 Register n um b er Auto decrement 100 Register n um b er Indexed basic 101 Register n um b er Indexed full 110 Register n um b er Absolute short 111 000 Absolute long 111 001 Relative basic 111 010 Relative full 111 011 Immediate or status register 111 100

  2. T ABLE C.2 Differences from Motorola terminology T erminology used in this book Motorola terminology Autoincrement Address register indirect with p ostincrement Auto decrement Address register indirect with predecrement Indexed basic Address register indirect with displacement Indexed full Address register indirect with index Relative basic Program coun ter with displacement Relative full Program coun ter with index

  3. T ABLE C.3 Notation for Table C.4 Symbol Meaning s Source operand d Destination operand An Address register n Dn Data register n Xn An address or data register, used as an index register PC Program counter SP Stack pointer SR Status register CCR Condition co de flags in SR AAA Address register n umber DDD Data register n umber rrr Source register n umber RRR Destination register n umber eeeeee Effective address of the source op erand EEEEEE Effective address of the destination op erand MMM Effective address mo de of destination CCCC Specification for a condition co de test P. . . P Displacement Q. . . Q Quick immediate data    SS Size: 00 b yte, 01 w ord, 10 long w ord (for most instructions)    01 b yte, 11 w ord, 10 long w ord (for MO VE and MO VEA instructions) VVVV T rap v ector n umber u Condition co de flag state is undefined (meaningless) d(An) Indexed basic addressing mode d(An,Xi) Indexed full addressing mode d(PC) Relative basic addressing mode d(PC,Xi) Relative full addressing mode

  4. Please see “portrait orientation” PowerPoint file for Appendix C Table C.4. 68000 instruction set Left side of page 1

  5. Please see “portrait orientation” PowerPoint file for Appendix C Table C.4. 68000 instruction set Right side of page 1

  6. Please see “portrait orientation” PowerPoint file for Appendix C Table C.4. 68000 instruction set Leftt side of page 2

  7. Please see “portrait orientation” PowerPoint file for Appendix C Table C.4. 68000 instruction set Right side of page 2

  8. Please see “portrait orientation” PowerPoint file for Appendix C Table C.4. 68000 instruction set Left side of page 3

  9. Please see “portrait orientation” PowerPoint file for Appendix C Table C.4. 68000 instruction set Right side of page 3

  10. Please see “portrait orientation” PowerPoint file for Appendix C Table C.4. 68000 instruction set Left side of page 4

  11. Please see “portrait orientation” PowerPoint file for Appendix C Table C.4. 68000 instruction set Right side of page 4

  12. Please see “portrait orientation” PowerPoint file for Appendix C Table C.4. 68000 instruction set Left side of page 5

  13. Please see “portrait orientation” PowerPoint file for Appendix C Table C.4. 68000 instruction set Right side of page 5

  14. Please see “portrait orientation” PowerPoint file for Appendix C Table C.4. 68000 instruction set Left side of page 6

  15. Please see “portrait orientation” PowerPoint file for Appendix C Table C.4. 68000 instruction set Right side of page 6

  16. T ABLE C.5 68000 branch instructions Mnemonic Displacement Operation (Name) size OP co de performed  BRA 8 0100 0000 PPPP PPPP PC [PC] disp + (Branch alw a ys) 16 0110 0000 0000 0000 PPPP PPPP PPPP PPPP Bcc 8 0110 If cc is true, then CCCC PPPP PPPP (Branch  conditionally) 16 0110 CCCC 0000 0000 PC [PC] disp + PPPP PPPP PPPP PPPP –  BSR 8 0110 0001 PPPP PPPP SP [SP] 4;  (Branch to [SP] [PC];  subroutine) 16 0110 0001 0000 0000 PC [PC] disp + PPPP PPPP PPPP PPPP DBcc 16 0101 CCCC 1100 1DDD If cc is false, then –  (Decremen t PPPP PPPP PPPP PPPP Dn [Dn] 1; –  and branc h If [Dn] 1, then  conditionally) PC [PC] disp + DBRA The assem bler in terprets this instruction as DBF (Decremen t (see the DBcc en try). and branc h)

  17. T ABLE C.6 Condition codes for Bcc, DBcc and Scc instructions Machine Condition code suffix CCCC cc Name Test condition 0000 T T rue Alw a ys true 0001 F F alse Alw a ys false  0010 HI High C Z = 0  0011 LS Lo w or same C Z = 1 0100 CC Carry clear C = 0 0101 CS Carry set C = 1 0110 NE Not equal Z = 0 0111 EQ Equal Z = 1 1000 V C Ov erflo w clear V = 0 1001 VS Ov erflo w set V = 1 1010 PL Plus N = 0 1011 MI Min us N = 1  1100 GE Greater or equal N V = 0  1101 L T Less than N V = 1   1110 GT Greater than Z (N V) = 0   1111 LE Less or equal Z (N V) = 1 T and F suffices cannot b e used in the Bcc instruction

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