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Getting Started with MPC560xB The Freescale Cup

MPC560xB. Getting Started with MPC560xB The Freescale Cup. Steve Mihalik January 24, 2011. Agenda – Getting Started with MPC560xB. MPC560xB. MPC5607B Overview. CORE Power Architecture e200z0 core running at 64MHz @ Ta=105C (48Mhz at 85oC Base)

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Getting Started with MPC560xB The Freescale Cup

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  1. MPC560xB Getting Started with MPC560xBThe Freescale Cup Steve Mihalik January 24, 2011

  2. Agenda – Getting Started with MPC560xB

  3. MPC560xB MPC5607B Overview

  4. CORE • Power Architecture e200z0 core running at 64MHz @ Ta=105C (48Mhz at 85oC Base) • VLE ISA instruction set for superior code density • Memory Protection Unit with 16 regions, 32byte granularity • 16 channel DMA controller • MEMORY • 1.5M byte embedded program Flash • 64K byte embedded data Flash (for EE Emulation) • Up to 64MHz non-sequential access with 2WS • ECC-enabled array with error detect/correct • 96Kbyte SRAM (single cycle access, ECC-enabled) COMMUNICATIONS • 6x enhanced FlexCAN • 10 x LINFlex • 6 x DSPI, 8-16 bits wide & chip selects • 1 x I²C ANALOG • Up to 52 ch 5V ADC (16x12-bit, 36x10-bit) resolution TIMED I/O • 16-bit eMIOS module, 64ch. OTHER • 32 Channel DMA Controller • Debug: Nexus 2+ • I/O: 5V I/O, high flexibility with selecting GPIO functionality • Packages: 100LQFP, 144LQFP, 176LQFP, 208MAPBGA* (TBD) • Boot Assist Module for production and bench programming MPC5607B (1.5MB Flash) System Integration Crossbar Masters Debug JTAG VReg PowerPCTM e200z0Core Nexus 2+ PIT 4ch 32b Power Mgt Oscillator DMA FMPLL Interrupt Controller CROSSBAR SWITCH Memory Protection Unit (MPU) 1.5M Flash I/O Bridge 96K SRAM Standby RAM Boot AssistModule (BAM) Crossbar Slaves 64K Data Flash Communications I/O System 6 DSPI 1 I2C 6 FlexCAN 10 LINFlex Up to 52ch ADC 16x12bit, 36x10 Bit eMIOS 64ch, 16 bit

  5. 0x6 Data Organization in Memory • All MPC560xB instructions are either 16 or 32 bits wide. • Power architecture is naturally Big Endian, but has switch for Little Endian • Examples: Load word from address 0x0 loads the word “ABCD” Load half word from address 0x6 loads the half word “GH”

  6. Start-Up Sequence • POR monitors internal voltage and de-asserts itself • Default clock is the 16MHz IRC • Boot configuration pins are sampled by the hardware - possiblity to go into e.g. serial boot mode • Hardware checks reset configuration half word (RCHW) • If hardware finds a valid RCHW (0x5A) it reads the 32-bit word at offset 0x04 = address where Start-Up code is located (reset boot vector). • Device is put in static mode if no RCHW is found!

  7. Flash and SRAM Overview FLASH features: • Up to 1.5MBCode Flash (MPC5607B) • Up to 64k Data Flash on MPC560xB; same emulated EEPROM concept for most products of the MPC560xB family (sectorization; software compatibility; memory mapping) • 64-bit programming granularity (can change value from 10 only) • Read-while-write with Code and Data Flash or by RWW feature • Erase granularity is Sector size • 64-bit ECC with single-bit correction (and visibility), double bit detection for data integrity RAM features: • User transparent ECC encoding and decoding for byte, half word, and word accesses • 32-bit ECC with single-bit correction (and visibility), double bit detection for data integrity • ECC is checked on reads, calculated on writes • CAUTION: ECC requires SRAM must be initialized by executing 32-bit write operations (32-bit word aligned) prior any read accesses • Done in initialization code before main

  8. Why did I get Reset? • Destructive Reset Sources: • Power On Reset • Software Watchdog • 2.7V Low-voltage detected • 1.2 Low-voltage detected in Power Domain 1 • 1.2 Low-voltage detected in Power Domain 2 • Status flag associated with a given ‘destructive’ reset event is set in the Destructive Event Status Register (RGM_DES) • Functional Reset Sources: • External Reset • Code or Data Flash Fatal Error • 4.5V low-voltage detected • CMU clock freq higher/lower than reference • FXOSC freq. lower than reference • FMPLL failure • Checkstop reset • Software reset • Core reset • JTAG initiated reset • Status flag associated with a given ‘functional’ reset event is set in the Functional Event Status Register (RGM_FES)

  9. Debug, Software & ToolsRAppID: Rapid Application Initialization and Documentation • RAppID PinWizard: • Wizard workflow to allocate pins to peripherals • Generates spreadsheet • Inputs to RAppID Init • Free utility • RAppID Init: • Generates initialization code for startup from CRT0 • Generates interrupt handler code & framework • Has ability to define section map and place code into any desired section

  10. Debug, Software & ToolsRAppID PinWizard Screenshot

  11. MPC560xB System Integration Unit Lite (SIUL)Pad Configuration, Simple I/O

  12. PeripheralsSIUL Introduction • Pad Control and IOMux configuration: • Intended to configure the electrical parametersand I/O signal multiplexing of each pad; • may simplify PCB design by multiple alternate input / output functions • General Purpose I/O (GPIO) ports: • Can write to GPIO data output pin or port • Can read GPIO data input pin or port • External interrupt management • Allows the enabling and configuration (such as filtering window, edge and mask setting) of digital glitch filters on each external interrupt pin

  13. PeripheralsSIUL Pad Control and IOMux configuration overview • Pad Control is managed through Pad Configuration Registers (PCRs) • IOMux configuration is managed through: • PCR Registers (output functionalities) • PSMI Registers (input functionalities)

  14. PCRn.SMC PAD n PCRn.WPE PCRn.WPS IP 3 IP 1 IP 2 IP 4 IP a SoC Safe Mode PCRn.OBE a) PCRn.ODE b) PCRn.APC PCRn.SRC ADC ch #… PCRn.IBE PCRn.PA PAD m PSMI.PADSEL SIUL Pad Control and IOMux config Pad Configuration Reg. (PCR) Pad Select Multiplexed Inputs (PSMI) reg.

  15. PeripheralsSIUL Pad Control and IOMux configuration 2/4 Alternate functions are chosen by PCR.PA bitfields: PCR.PA = 00 -> AF0; PCR.PA = 01 -> AF1; PCR.PA = 10 -> AF2; PCR.PA = 11-> AF3. This is intended to select the output functions; For input functions, PCR.IBE bit must be written to ‘1’,regardless of the values selected in PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as “--”.

  16. PAD j PAD k IP “n+1” PAD l PeripheralsPSMISIUL Pad Control and IOMux configuration 3/4 PAD m PSMIn_n+3 Register

  17. PeripheralsSIUL Pad Control and IOMux configuration 4/4 • Different pads can be chosen as possible inputs for a certain peripheral function.

  18. PeripheralsSIUL GPIO Functionality SIUL PAD Control PCR Regs PSMI Regs GPIO functionality Data IOMux & PADs Pad Inputs Ext. Interrupt Mgmt Interrupt Controller • Interrupt config • Glitch filter

  19. SIUL General Purpose I/O • GPIO pads can be managed two ways: • On individual base (R/W access to a single GPIO); • Access is done on a byte basis • On port base (parallel access). • Ports accesses can be: • Data Read: 32-bit, 16-bit or 8-bit accesses • Data Write: 32-bit, 16-bit or 8-bit (only if not masked access) • Masked Access:This mechanism allows support for port accesses or for bit manipulationwithout the need to use read-modify-write operations Code example for writing to individual GPIO pin: SIU.PCR[68].B.PA = 0; /* Port E4 pin: Pad Assignment is GPIO */ SIU.PCR[68].B.OBE = 1; /* Port E4 pin: Output Buffer Enabled */ SIU.GPDO[68].R = 1; /* Port E4 pin: write 1 to Data Output */

  20. MPC560xB Clocks

  21. Platform Overview – Clocks • Clock Sources for Code Execution, System Clock (sysclk) • 4-16 MHzExternal Crystal/Oscillator-> FXOSC • Input to phase lock loop (FMPLL) to generate up to 64 MHz sysclk • FMPLL has frequency modulation option to reduce EMC • 16 MHz Internal RC Oscillator -> FIRC • Default system clock after Reset • Trimable • Low Power Clock Sources • 32 KHz External Crystal/Oscillator -> SXOSC • Low power oscillator • Dedicated for RTC/API • 128 KHz Internal RC Oscillator-> SIRC • Dedicated for RTC/API and watchdog • Trimable

  22. Platform overview – Clocks • Clock MonitorUnit (CMU) for • PLL clock monitoring : detect if PLL leaves an upper or lower frequency boundary • Crystal clock monitoring : monitors the external crystal oscillator clock which must be greater than the internal RC clock divided by a division factor given by RCDIV[1:0] of CMU_CSR register. • Frequency meter : measure the frequency of one clock source versus a reference clock. • CMU “event” (failure) will cause reset, SAFE mode request or interrupt request

  23. Platform overview – ClocksMPC560xB CGM Clocking Structure System Clock Selector (ME) Core Platform FXOSC_DIV SYSCLK FXOSC 4-16MHz div 1 to 32 FIRC_DIV FIRC 16MHz div 1 to 32 Peripheral Set 1 div 1 to 16 FMPLL Peripheral Set 2 div 1 to 16 FIRC RESET SAFE INT CMU Peripheral Set 3 div 1 to 16 FXOSC 32KHz 128KHz SXOSC SIRC FIRC_DIV API / RTC SXOSC_DIV SXOSC 32KHz div 1 to 32 SIRC_DIV div 1 to 32 SIRC 128KHz SWT (Watchdog) FXOSC CLKOUT Selector FIRC CLOCK OUT div 1/2/4/8 FMPLL

  24. Core Platform SYSCLK System Clock Selector (ME) FXOSC FXOSC_DIV Peripheral Set 1 Enable & div 1 to 16 FIRC FIRC_DIV Peripheral Set 2 Enable & div 1 to 16 FMPLL Peripheral Set 3 Enable & div 1 to 16 Platform overview – ClocksMPC560xB CGMSystem Clock • Provides the clock (divided or not) to the Core/Peripherals • Selected by ME_XXX_MC register (XXX is desired mode) in the Mode Entry (ME) module

  25. Platform overview – ClocksMPC560xB CGM System Clock Divider Configuration Register Peripheral Set 1 Peripheral Set 2 Peripheral Set 3 All LINFlex modules All FlexCAN modules All eMIOS modules I2C module All DSPI modules CTUL ADC DEx: Peripheral Set x Divider Enable (Default value 1 = ON) DIVx: Peripheral Set xDivider x Division Value (1..15)

  26. Platform overview – ClocksMPC560xB CGM Output Clock Description • Clock output on the GPIO[0] (PA[0]) pin Watch out: max pad slew rate! FXOSC CLKOUT Selector CLOCK OUT (GPIO[0]) FIRC div 1/2/4/8 FMPLL SELDIV: division by 1, 2, 4, 8 SELCTL: clock source (XOSC, FIRC, PLL) selection

  27. CGMFMPLLNormal mode The PLL output clock frequency derives from the relation: (FXOSC x NDIV) (IDF x ODF) FMPLL = Input divider 1..15 Output divider 2/4/8/16 4 4MHz 128MHz FMPLL 2 64MHz 16MHz 32 Loop divider 32..96 Example: FXOSC = 16MHz FMPLL = 64MHz  NDIV = 4 * IDF * ODF  NDIV = 32 , IDF = 4 , ODF = 2

  28. CMU Ref.: Clock Monitor Unit Tasks • The first task of the CMU is to permanently supervise the integrity of the various product’s clock sources, e.g. FXOSC or FMPLL, if either • FXOSC clock frequency lower than FIRC / 2n • PLL clock frequency upper or lower frequency boundaries defined in CMU registers • If an integrity problem occurs, the Mode Entry module is notified in order to switch to SAFE mode with FIRC as clock source. • The second task is frequency measurement. It allows to measure the deviation of a clock (FIRC, SIRC or SXOSC ) by measuring its frequency versus FXOSC as reference clock. • Can be used to improve IRC calibration • Can be used for Real Time Counter precision

  29. RGM, ME FXOSC Failure FXOSC supervisor FFXOSC< FFIRC / 2RCDIV FXOSC FIRC FXOSC stable/unstable CMU_ISR register CMU Ref.: Crystal Clock Monitor • Crystal clock monitor is active only when ME provides the info that FXOSC is valid • If FXOSC < FIRC / 2RCDIV (CMU_CSR[RCDIV] bits), then • an event pending bit CMU_ISR[OLRI] is set. • a failure event is signaled to the RGM which in turn can generate a RESET, transition to SAFE mode, or generate an interrupt request

  30. CMU Ref.: Crystal Clock Monitor Reset Default Values • CAUTION: Before enabling crystal clock input in a mode configuration, verify the proper compare frequency divider. • MPC560xB, MPC560xS: reset default RCDIV = 3, so FreqFIRC / 2CMU_CSR[RCDIV] = 16 MHz / 8 = 2 MHz • MPC560xP: reset default RCDIV = 0, so FreqFIRC / 2CMU_CSR[RCDIV] = 16 MHz / 1 = 16 MHz

  31. CMU Ref.: Crystal Clock Monitor Event Behavior • Oscillator Less than Reference event occurs when the FXOSC appears too slow and sets: • CMU_ISR[OLRI] • No interrupt or other automatic action can be generated – just sets the bit • RGM_FES[F_CMU_OLR] • Action taken is per table below:

  32. CMU Ref.: FMPLL Monitor – Frequency Range • FMPLL monitoring is enabled at CMU_CSR(CME) • Monitoring is active only when ME provides the info that FMPLL is valid. • Depending on the following conditions • If FFMPLL is lower than HLREF[11:0] bits in CMU_LFREFR • If FFMPLL is higher than HFREF[11:0] bits in CMU_HFREFR

  33. CMU_HFREF register ME, RGM Fpll > LHREF threshold FMPLL FMPLL Failure FIRC Fpll < LFREF threshold FMPLL stable/unstable CMU_LFREF register CMU_ISR register CMU Ref.: FMPLL Monitor – Failure Behaviour • Then for each matching: • a dedicated event pending bit in CMU_ISR is set. • a failure event is output to the RGM & ME which can generate a transition toSAFE mode, an interrupt or a reset sequence.

  34. MPC560xB RUN Modes Introduction

  35. Use Case: Conserving Power While Software Runs (1 of 2) • Software runs one of the three following tasks: • Analog Monitor • Uses ADC to look for particular voltages on inputs • Only requires 16 MHz FIRC, which is also sysclk • If analog input measurements meet a criteria, software transitions to the communication task • Communication • Uses FlexCAN_0, FlexCAN_1 to transmit analog data and receive response • Only requires FXOSC, which is also sysclk • If response is positive, software transitions to the whole chip task • Whole Chip • Requires all peripherals active • Sysclk = 64MHz FMPLL, which also requires FXOSC

  36. Use Case: Conserving Power While Software Runs (2 of 2)

  37. Mode Overview • The Mode Entry Module (MC_ME) provides SYSTEM modes and USER modes : • SYSTEM: RESET, DRUN (Default RUN), SAFE and TEST • USER: RUN(0..3), HALT, STOP and STANDBY • For each mode the following parameters are configured/controlled • System clock sources (ON/OFF) • System clock source selection • Flash power mode (ON, low power, power down) • Pad output driver state (For low power modes - can disable Pad Output drivers, enabling high impedance mode) • Peripherals’ clock (gated/clocked)

  38. HW triggered transition SW triggered transition Device Modes - Diagram USER MODES SYSTEM MODES LOW POWER MODES RUN 0 Recoverable HW failure SW request SAFE HALT RUN 1 RESET DRUN STOP RUN 3 TEST Non recoverable HW failure STANDBY

  39. 11 12 13 14 15 3 0 2 4 5 7 8 9 10 1 6 MVR MVR reserved reserved PDO PDO reserved reserved DFLAON DFLAON CFLAON CFLAON ON ON 16 17 30 18 23 24 25 29 31 19 20 21 22 26 27 28 PLL PLL OSC OSC IRC IRC reserved SYSCLK SYSCLK ON ON ON ON ON ON ME_xxx_MC - Mode Configuration Registers • Each mode has a Mode Configuration register. • Example: ME_DRUN_MC • Key RUN mode configurations are circled: • PDO: Disable pad outputs (put in hi Z) • MVRON: control VREG on/off • CFLAON/DFLAON: • control code / data flash module • Normal • Low Power • Power Down • PLLON: control PLL on/off • OSCON: control XOSC on/off • IRCON: control IRC16M on/off • SYSCLK: select system clock

  40. Mode Configurations Example • It is useful to keep a table of mode configurations used. • Example below uses two USER modes. (Per AN2865 rev 4)

  41. Peripheral Clock Gating Control • Each peripheral can be associated with a particular clock gating policy • The policy is determined by two groups of peripheral configuration registers: • ME_RUN_PC0:7 for RUN modes • ME_LP_PC0:7 for Low Power modes • Clocks to peripherals are gated off unless enabled for that mode • Example (per AN2865 rev 4):

  42. MC_ME Peripheral Configuration RegistersRUN Modes Defines a selection of 8 possible RUN mode configurations for a peripheral

  43. Device Start-up:MC_ME Peripheral Control Registers For each peripheral, there is a ME_PCTLx register to control clock gating to that peripheral: - selects one of the 8 Run peripheral set configurations - selects one of the 8 Low Power peripheral set configurations - enables/disables freezing the clock during debug Peripheral 143 Peripheral 3 Peripheral 2 Peripheral 1

  44. Mode Entry: SW and HW Transitions • Software handled transition • A transition is requested writing a key protected sequence in ME_MCTL • Mode Entry configures the modules according to the ME_xxx_MC register of the target mode • Once all modules are ready the new mode is entered • Transition completion signalling: status bit/interrupt • Note: Modification of a ME_xxx_MC register (even the current one) is taken into account on next mode “xxx” entry • Hardware triggered transition • Exit from low power mode • SAFE transition caused by HW failure • RESET transition caused by HW failure

  45. Review of Key Points • RUN mode configurations allow • Enabling/disabling system clock sources • Selecting appropriate system clock • Gating clocks to peripherals • Peripheral clocks can be divided as needed on a set basis • Example PLL: Initializing System Clock

  46. Exercise: Initialize PLL & RUN Mode, Write GPIO Output • Open existing CodeWarrior Project, “PLL-sysclk” • Navigate to the PLL-sysclk project for MPC560xB. Example path: C: \ Program Files \ Freescale \ CW for MPC55xx and MPC56xx 2.7 \ (CodeWarrior_Examples) \ 560xB-CW \ PLL-sysclk • Double click on the project file “PLL-sysclk.mcp” to open it in CodeWarrior • Compile and link RAM project • Either a) click: Project – Make – or-- b) click on the make icon • Download to target • Connect EVB to PC with USB cable • Either click: Project – Debug, or, click on the Debug icon • Click the “Connect” button • Type “gotil main” in the Status Window • Initialize registers to turn on LED1 on target board • Click the “REG” button at the top • Click “SIUL System Integration Unit Lite” • Set bit fields for a GPIO output (PCR68: PA=1, OBE=1; GPDO68: PDO=1) • Exit register windows then open again to validate the register was altered • Are registers still shown as modified? Execute thru initModesAndClock &re-try.

  47. MPC560xB Timed I/O (Watchdog, PIT & eMIOS)

  48. Watchdog Timer – Regular Mode Servicing • To prevent the watchdog from interrupting or resetting, the following sequence must be performed before a timeout period: • Write 0xA602 to the SWT_SR • Write 0xB480 to the SWT_SR Note: other instructions, such as an ISR, can occur between above writes

  49. Programmable Interrupt Timer (PIT) Features • Clocked by system clock • 32-bit counter • Independent timeout periods for each timer • Timer can generate interrupt/DMA request, ADC conversion

  50. e200z0h Core Debug IRC 16M IRC 128K Integer Execution Unit General Purpose Registers (32 x 32-bit) (C)JTAG OSC 32K OSC 4-16M Multiply Unit BranchUnit PLL Instruction Unit VLE Load/StoreUnit VREG INTC Crossbar Switch (XBAR) Memory Protection Unit (MPU) 8 regions RAM Controller FLASH Controller Peripheral Bridge SWT STM 4 ch DSPI 2 - 4 eMIOS-lite 24 – 56 ch SRAM (ECC) Code Flash (ECC) PIT 6 ch I2C 1 BCTU FlexCAN 1 - 6 API/RTC SIU ADC10 16 – 57 ch LINFlex 3 - 8 Data FLASH (ECC) eMIOS260Introduction • Provides various modes to generate or measure timed event signals. • 24 to 56 Channels • One new channel mode featuring lighting applications, OPWMT • All other channel modes are subset of the unified channel structure on previous eMIOS. • Consistent user interface with previous eMIOS implementation.

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