Topics

1. Topics • Modeling with hardware description languages (HDLs).

2. Hardware description languages • Textual languages for describing hardware: • structure; • function. • Most people today use textual languages rather than schematics for most digital design. • Schematics make poor use of screen space.

3. Major HDLs • Two major HDLs designed for simulation: • VHDL; • Verilog. • Similar capabilities but somewhat different language philosophies. • EDIF is a standard netlist format.

4. Simulation vs. programming • Simulation tags computations with times. • Must know when signals change to properly simulate hardware. • Simulation is parallel. • Many statements can execute at the same (simulation) time. • Just like hardware.

5. Types of simulation • Compiled code simulation. • Generate program that evaluates a hardware block. • Operational details within the hardware block are lost. • Event-driven simulation. • Propagate events through simulation. • Don’t simulate a block until its inputs change.

6. An event is a change in a net’s value. An event has two components: value; time. Event-driven simulation net1 t=35 ns time net net1=0 @ 35 ns event

7. Propagate events only when nets change value. If an input change doesn’t cause an output change, no event is propagated. 1 no event 0 0 Events on a gate 0 1 1

8. Timewheel • The timewheel is a data structure in the simulator that efficiently determines the order of events processed. • Events are placed on the timewheel in time order. • Events are taken out of the head of the timewheel to process them in order.

9. c=0 @ 2 ns b=1 @ 1 ns 0 1 Timewheel operation a c 1 1 time 0 b a=1 @ 0 ns netlist timewheel

10. Order of evaluation • Order of evaluation is important. • Causality must be obeyed. • Evaluating events in the wrong order can cause inaccurate results.

11. e=0 @ 4 ns 0 d=1 @ 2 ns 1 b=1 @ 1 ns 1 Order of evaluation example a c 0 1 1 0 e time b 0 d netlist timewheel

12. Compiled simulation • A block of code is generated to simulate a block of hardware. • Can use compiler to optimize the code. • Code ignores much temporal behavior within the block. • Must still evaluate events in the right order. • Must generate times at interface to event-driven model.

13. Modeling • Structural modeling describes the connections between components. • Netlists are structural models. • Behavioral models describes the functional relationship between inputs and outputs. • Similar to programming but values are events.

14. HDLs language constructs • Must be able to define component types. • A model may be behavioral or structural. • May be able to define abstract data types. • A wire may carry an enumerated value. • Multi-valued simulation may be defined using abstract data types. • May be able to define modules to control the scope of names.

15. Testbenches • A testbench is a model used to exercise a simulation. • Provides stimulus. • Checks outputs. • Testbenches help automate design verification. • Rerun edited module against testbench. • Run models at behavioral, RTL levels against the same testbench.

16. Synthesis subsets • VHDL and Verilog were designed for simulation. • A synthesis subset is: • synthesizable; • produces consistent simulation results. • Different tools may use different synthesis subsets.

17. Register-transfer synthesis • Most common type of synthesis. • Synthesizes gates from abstract RT model. • Registers are explicit. • Some tools will infer storage elements---be careful. • Optimized for performance, area, power.