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CSC runs at minus side slice test 27 Mar. 2007 – 5 Apr. 2007

CSC runs at minus side slice test 27 Mar. 2007 – 5 Apr. 2007. Greg Rakness University of California, Los Angeles. Color scheme: Successes Problems/questions. Run 57012. 250k events; trigger=singles ME-3/2/19 Report from DQM… All unpacked events: do have this chamber in readout 100%

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CSC runs at minus side slice test 27 Mar. 2007 – 5 Apr. 2007

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  1. CSC runs at minus side slice test 27 Mar. 2007 – 5 Apr. 2007 Greg Rakness University of California, Los Angeles • Color scheme: • Successes • Problems/questions G. Rakness (UCLA)

  2. Run 57012 • 250k events; trigger=singles ME-3/2/19 • Report from DQM… • All unpacked events: • do have this chamber in readout 100% • with all boards (ALCT, TMB, CFEB) present 100% A. Korytov (Florida) G. Rakness (UCLA)

  3. Run 57013 • 1M events; trigger = singles on all chambers • Trigger signals at Sector Processor (K. Kotov, Florida): • timed to within 0.2bx, except… • ME-3/1/10 ~ 0.6bx • Settings based on AFEBALCT and ALCTTMB cable lengths successful (M. Ignatenko, UCLA) • Data from ME-2/2/16 ALCT is bad, found to be ALCT and/or skew-clear cable. Remove ME-2/2/16 from data acquisition path… (Note: trigger = singles on all chambers for runs discussed today) G. Rakness (UCLA)

  4. ALCT0_BXN - L1A_BXN: PERFECT A. Korytov (Florida) • Run 57013: ALCT0-L1A BXN difference = 3, 4 • Run 539: ALCT0-L1A BXN difference = 3 (the same for all!) [Value of xml parameter alct_l1a_delay: Run 57013 = constant value Run 539 = set for each chamber to be value measured with scan] UF group 29 March 2007 4

  5. Raw anode hits: PERFECT Run 539: Anode hits for all chambers are captured right in the middle of the 0-15 window (average is ~7.5 for all chambers) A. Korytov (Florida) Time bin 7.5 ALCT wiregroup [Formula by J. Hauser (UCLA) and A. Madorsky (Florida): If alct_l1a_delay has been timed in to be in the middle of the ALCT L1A window, then the number of time bins before pretrigger is equal to (alct_fifo_pretrig-6)+(alct_l1a_window_size-1)/2.] UF group 29 March 2007 5

  6. CLCT0_BXN - L1A_BXN: no changes A. Korytov (Florida) • CLCT0-L1A BXN difference = -1, 0 • [No change observed, even though the setting for tmb_l1a_delay did change: • Run 57013 = constant for all chambers • Run 539 = value measured by TMB-L1A delay scan • Why?] UF group 29 March 2007 6

  7. Upgrade TMB firmware to 9 January 2007 version • ISE compiled • bug fix on 2nd CLCT • zero dead-time triad decoders Run 542: Data look good with ISE compilation… …(relatively minor) issues of word count in DMB data quality check… Go back to 5 September 2006 version (MTCC version)… A. Korytov (Florida) G. Rakness (UCLA)

  8. ME-3/1/8 ME-2/1/8 • Upgrade ALCT firmware to 2 April 2007 version… • modified timing of mux clock/control Runs 546, 547: Run 547: smooth distributions Run 57013: “ratty” anode wiregroup occupation histograms… A. Korytov (Florida) • Run 547 = HV on ring 1 chambers only, in order to trigger only on ring 1 • CRC errors persist (<0.1/mil on 8/16, ~1% on 1/16)  cable at CFEB? Fiber? G. Rakness (UCLA)

  9. Upgrade peripheral crate software w/expanded TMB, ALCT, DMB configuration from xml • TMB/ALCT config verified with “check configuration” button • Upgrade ME-3/1 with ALCT576mirror firmware v.02Apr07 Run 546: Run 552: ME-3/1/8 ME-3/1/8 Run 552: A. Korytov (Florida) • Wiregroup distributions look good (begin at 1, end at 96) • “Complete set” of parameters available to study trigger configurations • ME-3/1/8 TMB was not triggering(similar occasional “slot 2 problem” seen during MTCC) G. Rakness (UCLA)

  10. To do: • update TMB firmware when available… • header update to solve word count issue • bit to turn off LCT  MPC (?) • begin implementing configure using hard reset • Does CSC handle it correctly? • TMB and DDU counters checked during MTCC, but data never taken… • Does ME-3/1/8 come back? • begin systematic study of trigger configuration (see Jay’s talk) G. Rakness (UCLA)

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