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SLHC CMS EMU Upgrade Digital CFEB

SLHC CMS EMU Upgrade Digital CFEB. Ben Bylsma The Ohio State University. Current CFEB. Basic Block Diagram:. SCA. ADC. FPGA. To DMB over Skewclear. +. 8 Triad signals. pre. 12 bits. 16. 16. Chan-link. -. ref. mux. 21 bits. 6 layers. 21:3. 280 Mbps.

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SLHC CMS EMU Upgrade Digital CFEB

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  1. SLHC CMS EMU UpgradeDigital CFEB Ben Bylsma The Ohio State University B. Bylsma, CMS Upgrade Workshop, FNAL, Oct. 28, 2009

  2. Current CFEB Basic Block Diagram: SCA ADC FPGA To DMB over Skewclear + 8 Triad signals pre 12 bits 16 16 Chan-link - ref mux 21 bits 6 layers 21:3 280 Mbps . . . . . . To TMB over Skewclear comp pre 3x8 2:1 LVDS 24 bits 24 bits X 80 Mbps . . . . . . 3x8 6 layers Time Line: Digitization and Readout Analog storage Analog storage - no coincidence Analog storage with L1A*LCT coincidence event LCT L1A ~3.2µS Release Caps ~20µS Analog samples are stored until L1A. Then ADC must digitize 8X16 samples one at a time. Limited number of capacitors and single channel ADC impose constraints on LCT and L1A latencies. B. Bylsma, CMS Upgrade Workshop, FNAL, Oct. 28, 2009

  3. New DCFEB DAQ Path Basic Block Diagram: Serial LVDS 8 pairs ref ADC ADC FPGA + + 16 8 8 pre To DMB over Fiber 16 pairs - - Pipeline/FIFOs Serial GTX Opt. Trnscvr 8 pairs ~1Gbps ref . . . 6 layers . . . DAQ path Digitization Latency Readout Time Line: Pipeline FIFO L1A·LCT event xfer LCT L1A 3.2 to 6.4µS 8 to 20µS No Dead Time. All 96 channels continuously digitized (no multiplexing). B. Bylsma, CMS Upgrade Workshop, FNAL, Oct. 28, 2009

  4. New DCFEB Trigger Path To TMB over Skewclear Current Design: 8 Triad signals 8 Triad signals 8 Triad signals 8 Triad signals 16 16 16 16 24 bits X 80 Mbps Latency: 1.5+3 clocks + fixed = 4.5-5 bx To TMB over Skewclear Option A: comp comp comp DS90CR483A 48 bit Channel link pre pre pre 6x8 3x8 48 48 bits Pre-emphasis DC balance Cable Deskew To TMB over Skewclear 2:1 LVDS Serial 24 bits GTX Opt. Trnscvr 8 LVDS X 280 Mbps ~2.56Gbps 6 layers 6 layers 6 layers . . . . . . . . . . . . . . . . . . 3x8 Latency: 86-113 ns To TMB over Skewclear comp Option B: pre 2x8 2:1 TLK2501 SER/DES 16 bits Opt. Trnscvr ~1.28Gbps 6 layers 2x8 . . . . . . 2x8 2:1 TLK2501 SER/DES 16 bits Opt. Trnscvr ~1.28Gbps 2x8 Latency: ? FPGA Option C: B. Bylsma, CMS Upgrade Workshop, FNAL, Oct. 28, 2009

  5. First Step – Choose ADC • ADC choice drives subsequent design considerations • Interface between pre-amp and ADC • Voltage/Power requirements • Could impact LVDB design • ADC choices:(8 ch, 12 bit, 20-65 MSPS, Serial LVDS output) • MAX1437 (Maxim) 1.8V supply, 1.4Vpp range • ADC12EU050 (National) 1.2V supply, 2.1Vpp range • AD9222 (Analog Devices) 1.8V supply, 2Vpp range • ADS5281 (Texas Instr.) 3.3V analog, 1.8V digital, 2Vpp range B. Bylsma, CMS Upgrade Workshop, FNAL, Oct. 28, 2009

  6. Issues with ADCs • None are suitable drop-in replacements for SCA/ADC • ADC’s • All have differential inputs • Limits on common mode • Have internal input bias network • Pre-Amp • Single ended output • Limited range of baseline level • Designed to drive small capacitive load • Pre-Amp/ADC Interface • Mnfr. suggest transformer coupling • (not an option for us) • Amplifier to generate differential signal • (requires 96 amplifiers) • Direct couple single ended signal • (common mode consequences) • (level shifting/scaling) • AC couple single ended signal • (common mode consequences) • (no level shifting, but still have biasing to consider) B. Bylsma, CMS Upgrade Workshop, FNAL, Oct. 28, 2009

  7. Constraints (ADS5281) • ADC Constraints: • Vcm -600mV < (IN+ + IN-)/2 < Vcm +300mV (1.8Vpp on IN+) • (IN- -1V) < IN+ < (IN-+1V)(ADC output range) • Pre-Amp Constraints: • Baseline Level • Currently 1.8V • Max ~2.0V • Min ~1.2V (maybe 1.0V) • Drive Capability • Small (few mA at best) • Scaling: • Scale down input • Add digital gain on output • Resistor divider 1.2k Vcm 1.2k B. Bylsma, CMS Upgrade Workshop, FNAL, Oct. 28, 2009

  8. Digitize Amplifier Pulses Connect CFEB to Evaluation Board: 50ns samples B. Bylsma, CMS Upgrade Workshop, FNAL, Oct. 28, 2009

  9. DCFEB Prototype • Build prototype with four options for preamp/ADC interface • Options include: • Direct Coupling with scaling • AC Coupling with scaling • Single to Differential with Analog Devices ADA4950 • Single to Differential with TI THS4524 • DAQ path: • Virtex 5 or 6 • Data sent in MAC level ethernet packets • Trigger path: • Three options (see slide 4) fiber or copper? • Major concern is additional latency (seems unavoidable) • Other concerns: additional components/power consumption • On TMB end: compatibility with mezzanine board B. Bylsma, CMS Upgrade Workshop, FNAL, Oct. 28, 2009

  10. Related Work • Changes on ME1/1 to accommodate DCFEBs: • 7 DCFEBs, same form factor (scheme exists) • Copper (and fiber) cables from DCFEBs to patch panel • New patch panel (copper cables 7 to 2) • New LVDB (power requirements TBD) • Peripheral Crate: • New DMB (PCB design relatively straight forward) • New TMB (dependent on comparator transfer scheme) • Decisions need to be made but should not be rushed B. Bylsma, CMS Upgrade Workshop, FNAL, Oct. 28, 2009

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