Electronic Troubleshooting

1. Electronic Troubleshooting Chapter 10 Digital Circuits

2. Digital Circuits • Key Aspects • Logic Gates • Inverters • NAND Gates • Specialized Test Equipment • MOS Circuits • Flip-Flops and Counters

3. Logic Gates • Characteristics • A combinational Logic circuit with two or more inputs and one output • OR Gates • And Gates • Exclusive OR Gates • etc. • Inputs are limited too two values • High –Logic 1 • Often assumed to be +5V • Low – Logic 0 • Often assumed to be 0V

4. Logic Gates • Characteristics • Inputs are limited too two values • Possible combinations • 2-inputs with 2-possible values => 4 permutations • Permutations 2n , n= number of inputs • OR Gate

5. Logic Gates AND Gate

6. Logic Gates Boolean algebra • Exclusive OR Gate • The XOR gate (sometimes EOR gate) is a digital logic gate that implements exclusive disjunction - it behaves according to the truth table • A HIGH output (1) results if one, and only one, of the inputs to the gate is HIGH (1). • If both inputs are LOW (0) or both are HIGH (1), a LOW output (0) results.

7. Logic Gates • Sample Gate Application • AND Gate • What would the Output be with: OR Gate, XOR Gate

8. Inverters • Characteristics • Changes one logic level to the other • Often needed in digital circuits • Chapter 9 page 248 • The “R” input to the flip-flop has an invert on it

9. Inverters Notice the line over BURST. It is called BURST NOT • Sample Application

10. NAND Gates • Key Aspects • Can be built with the gates already covered • An AND Gate followed by an Inverter • So commonly used construction – are available monolithic implementations • Characteristics

11. In Class Review • Combination Logic and Truth Tables • Problem 10-2 on page 293 • Problem 10-5 on page 293 • Simple Troubleshooting • Problem 10-3 on page 293

12. Actual Gate Considerations • Key Aspects • Will use NAND Gates as a sub fro all gates • Simplified /Improved Component Count • Two emitters almost as easy in manufacturing as one • Accomplished when artwork for the IC is made • Less components • Q1 functions like the three diodes it replaced, not as an amplifier

13. Actual Gate Considerations • Rise Time Problems • Caused by the input capacitance of gates driven high • TTL gates typically have a Fan out of 10 • Thus the parallel connection the gate’s input capacitance is significant • Rise time will decrease if R2 was made smaller • However significant current would flow when Q2 was turned on

14. Actual Gate Considerations • Rise Time Problems • Solution • Use Totem Pole Output • Totem Pole Operation • When at least on input is low • Q2 is off, No current in R3 and Q4 is off • Q3 is on and R4 can be small and minimize the time constant for the output to go high • With a Low out Q3 is off • When both inputs are High • Reverse currents supply base of Q4

15. Actual Gate Considerations • Rise Time Problems • Totem Pole Operation • When both inputs are High • Reverse currents supply base of Q2, Q2 conducts • Base of Q4 goes high and Q4 conducts • Output is Low • Much faster Rise times • Since Q3 only conducts when the output is high, R3 can be sized to minimize the time constant and not cause a heat and efficiency problem

16. Actual Gate Considerations Typical TTL parameters

17. Actual Gate Considerations Typical TTL part - 7400

18. Actual Gate Considerations • Standard 74 series TTL has evolved into other series: • Standard TTL, 74 series • Schottky TTL, 74S series, Low power Schottky TTL, 74LS series (LS-TTL), Advanced Schottky TTL, 74AS series (AS-TTL), Advanced low power Schottky TTL, 74ALS series • 74F fast TTL • CMOS series • CD 4000, incompatible with TTL voltage levels • Low power CMOS 74 series pin compatible, 74LS series • Low power CMOS that is TTL level and pin compatable – 74HCT, • Improved versions, e.g., LV, LVT, ALVT, AC/ACT (A is for advanced, T is for TTL compatable)

19. Specialized Test Equipment • Logic Probe • Example: Instek GLP-1A Logic Probe

20. Specialized Test Equipment • Digital Pulser • Digital Pulser (SJ-1) • Accurate Timebase Generator • Output: Open Collector • (Interfaceable with any Logic Circuits) • Supply: 4.5V-18VDC • 9 Selectable Output Frequencies: 16MHz (crystal osc. output), 8MHz, 1MHz, 100KHz, 10KHz, 1KHz, 100Hz, 10Hz & 1Hz.

21. Specialized Test Equipment Logic Analyzere

22. Specialized Test Equipment Testing a gate in a Live Circuit

23. MOS Circuits • Characteristics • Most common type is CMOS – Complementary MOS • Circuits use both P-Channel and N-Channel devices in the same circuit • CMOS Circuits consume very little power • Most of the TTL logic gates have been implemented in CMOS • Typical Gates covered • Inverters and NOR gates • Inverter • Same logic symbol as for the TTL version • Same truth table

24. MOS Circuits • Inverter • Circuit Operation • With the input at ground – Logic 0 • 0V Gate-source on the N-Channel device (Q2) and it is off • -Vdd Gate to-Source on Q1 and it is on and acts like a 1000 Ω resistor • Vdd on the output • With the input high – Logic 1 • Q2 conducts and appears as a 1000 Ω resistor • Q1 is off and appears as an open

25. MOS Circuits • NOR Gate • Characteristics • Refer to Figure 10-16 on page 281 of the textbook • Logic table • Logic 1 out only with all logic 0s on the input • Construction • Two P channel MOSFETs connected to the inputs and connected in series with the VDD and the output • Two N channel MOSFETs connected to the inputs and in parallel between the output and ground • Circuit Operation • With both inputs at ground – A & B at Logic 0 • Q1 and Q2 (P channel devices) turn on and conduct • Q3 and Q4 (N channel devices) are open and not conducting • - VDD appears at the Output

26. MOS Circuits • NOR Gate • Circuit Operation • With both inputs, A & B at Logic 0 • Q1 and Q2 turn on and conduct • Q3 and Q4 are open and not conducting • - VDD appears at the Output • With either or both A & B at Logic 1 • Either Q1 or Q2, or both are turned off and not conducting much • Either Q3, Q4, or both are turned on and conducting • Logic 0 appears at the Output • CMOS Characteristics • See chart on the next slide • Handling Precautions – see top of page 283

27. MOS Circuits CMOS Characteristics

28. In Class Review • Logic Levels • Logic Level References • Problem 10-1 on page 292 using TTL levels • Problem 10-1 on page 292 using 5V CMOS • Open Inputs • Problem 10-13 on page 295 • Fan Outs • Problem 10-15 on page 295 • Problem 10-16 on page 295 • Problem 10-17 on page 296 • Problem 10-18 on page 296

29. Flip-Flops and Counters • Characteristics • Used to make sequential logic circuits • Outputs depend upon: • A previous event • Combinational logic inputs • The circuits remember what has happened • Covered topics • RS Flip-Flops • D Flip-Flops • J-K Flip-Flops • Binary and Decade Counters • 7-Segment displays

30. Flip-Flops and Counters • RS Flip-Flops • Can be implemented using NAND, NOR, AND, OR, and Inverters • NOR gate Implementation • Lower right drawing • Used ½ of a 7402 IC • Inputs are Active Highs • A high input will change the state of the Gate • NAND gate Implementation • Used ½ of a 7400 IC

31. Flip-Flops and Counters • RS Flip-Flops • NAND gate Implementation • Notice on the circuit and the logic symbol – Active Low inputs • A Low input will change the state of the Gate • A High input will not effect the output • Other implementations use • AND & OR gates with inverters • See NAND Gates below

32. Flip-Flops and Counters • RS Flip-Flops • NAND Gate version • Alternate Logic symbol drawing • Also – Pull-Up Resistor

33. Flip-Flops and Counters • D Flip-Flops • Operation • Logic symbol arrows indicate I/O • PR and CLR act like the Set (S) and Reset (R) inputs on a NAND Gate R-S Filip-Flop • Q and Q are always in opposite states • The input CK (clock) on a positive transition causes Q to go either high or low depending on the D input • Q’s state will match the state of D at that time

34. Flip-Flops and Counters • J-K Flip-Flops • Operation • Has same PR and CLR as type D • Has two inputs J and K instead of the D input • See the truth Table • Has an additional MODE of operation – Toggle • Outputs will toggle when a new clock pulse arrives at the CK pin • Bubble on the CK indicates that negative transition is active

35. Flip-Flops and Counters Walk through the circuit and timing diagram • Binary Counter using J-K Flip-Flops • Q output acts as the clock input to the next Flip-Flop

36. Flip-Flops and Counters • Sample Monolithic Counter • 7493 • Can be a 3-bit or 4-bit counter • Wire QA output to input B for 4-bit • MOD 16 counter • Otherwise use input B • MOD 8 counter • 14 – pin DIP

37. Flip-Flops and Counters http://www.datasheetcatalog.org/datasheet/nationalsemiconductor/DS006533.PDF • Sample Monolithic Counter • 7490 • Decade counter • Counts 0 – 9 and can be reset to zero • Has 4 outputs • Reference

38. Flip-Flops and Counters • BCD Displays • A common Anode version is shown • Common Cathode versions are also available

39. Flip-Flops and Counters • Interface Circuit • The BCD counters output binary that resets after 9 • The 7 segment display with decimal point has eight inputs that cause numbers 0-9 to display • The 7447 is a seven segment display driver that translates binary counts into a seven segment inputs • See pages 291 and 292

40. In Class Review • Timing • Problem 10-19 on page 296 • Identifying problems in Digital Circuits • Problem 10-21 on page 297 • Problem 10-22 on page 298 • Problem 10-23 on page 298 • Problem 10-27 on page 298