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Verilog for Digital Design

Verilog for Digital Design. Chapter 3: Sequential Logic Design. 3.1. Introduction. Sequential circuit Output depends not just on present inputs (as in combinational circuit), but on past sequence of inputs Stores bits, also known as having “state”

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Verilog for Digital Design

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  1. Verilog for Digital Design Chapter 3: Sequential Logic Design

  2. 3.1 Introduction • Sequential circuit • Output depends not just on present inputs (as in combinational circuit), but on past sequence of inputs • Stores bits, also known as having “state” • Simple example: a circuit that counts up in binary • In this chapter, we will: • Design a new building block, a flip-flop, that stores one bit • Combine that block to build multi-bit storage – a register • Describe the sequential behavior using a finite state machine • Convert a finite state machine to a controller – a sequential circuit having a register and combinational logic 1 a 1 Combinational digital circuit F 0 b 1 a ? Sequential digital circuit F 0 b si ansis Must know sequence of past inputs to know output e z Note: Slides with animation are denoted with a small red "a" near the animated items

  3. Call button Blue light Bit Storage Cancel button Blue light Call button Bit Storage Cancel button Q Call 2. Call button released – light stays on Cancel Call button Blue light Bit Storage Doesn’t work. Q=1 when Call=1, but doesn’t stay 1 when Call returns to 0 Cancel button Need some form of “feedback” in the circuit 3. Cancel button pressed – light turns off 3.2 Example Needing Bit Storage • Flight attendant call button • Press call: light turns on • Stays on after button released • Press cancel: light turns off • Logic gate circuit to implement this? 1. Call button pressed – light turns on a a

  4. Freq Period 100 GHz 0.01 ns 10 GHz 0.1 ns 1 GHz 1 ns 100 MHz 10 ns 10 MHz 100 ns Clocks • Clock period: time interval between pulses • Above signal: period = 20 ns • Clock cycle: one such time interval • Above signal shows 3.5 clock cycles • Clock frequency: 1/period • Above signal: frequency = 1 / 20 ns = 50 MHz • 1 Hz = 1/s

  5. rising edges Clk D flip-flop D latch D latch Q ’ D Dm Qm Ds Q s ’ Q Cs C m Qs master servant Clk D Flip-Flop • Flip-flop: Bit storage that stores on clock edge, not level • One design -- master-servant • Two latches, output of first goes to input of second, master latch has inverted clock signal • So master loaded when C=0, then servant when C=1 • When C changes from 0 to 1, master disabled, servant loaded with value that was at D just before C changed -- i.e., value at D during rising edge of C Note: Hundreds of different flip-flop designs exist

  6. rising edges Clk D Q ’ Q D Flip-Flop Internal design: Just invert servant clock rather than master D Q ’ The triangle means clock input, edge triggered Q Symbol for rising-edge triggered D flip-flop Symbol for falling-edge triggered D flip-flop falling edges Clk

  7. T Y D1 Q1 D2 Q2 D3 Q3 D4 Q4 w fli o l a t Clk Clk_A Clk_B D Flip-Flop • Solves problem of not knowing through how many latches a signal travels when C=1 • In figure below, signal travels through exactly one flip-flop, for Clk_A or Clk_B • Why? Because on rising edge of Clk, all four flip-flops are loaded simultaneously -- then all four no longer pay attention to their input, until the next rising edge. Doesn’t matter how long Clk is 1. Two latches inside each flip-flop

  8. C all Blue light Flight attendant call-button system but t on C an c el but t on C all Blue light but t on D Q’ C an c el but t on Clk Q Flight-Attendant Call Button Using D Flip-Flop • D flip-flop will store bit • Inputs are Call, Cancel, and present value of D flip-flop, Q • Truth table shown below Preserve value: if Q=0, make D=0; if Q=1, make D=1 Circuit derived from truth table, using Chapter 2 combinational logic design process Cancel -- make D=0 Call Cancel Call -- make D=1 Q Let’s give priority to Call -- make D=1

  9. Basic Register • Typically, we store multi-bit items • e.g., storing a 4-bit binary number • Register: multiple flip-flops sharing clock signal • From this point, we’ll use registers for bit storage • No need to think of latches or flip-flops • But now you know what’s inside a register

  10. Present 1 hour ago 2 hours ago Display Display Display b4 b3 b2 b1 b0 c4 c3 c2 c1 c0 a4 a3 a2 a1 a0 x4 e x3 r tu x2 a r TemperatureHistoryStorage x1 sensor x0 empe t timer C Example Using Registers: Temperature Display • Temperature history display • Sensor outputs temperature as 5-bit binary number • Timer pulses C every hour • Record temperature on each pulse, display last three recorded values (In practice, we would actually avoid connecting the timer output C to a clock input, instead only connecting an oscillator output to a clock input.)

  11. a4 a3 a2 a1 a0 b4 b3 b2 b1 b0 c4 c3 c2 c1 c0 I 4 Q4 I 4 Q4 I 4 Q4 x4 I 3 Q3 I 3 Q3 I 3 Q3 x3 I 2 Q2 I 2 Q2 I 2 Q2 x2 I 1 Q1 I 1 Q1 I 1 Q1 x1 I 0 Q0 I 0 Q0 I 0 Q0 x0 R a R b R c C TemperatureHistoryStorage 15 18 20 21 21 22 24 24 24 25 25 26 26 26 27 27 27 27 x4...x0 C 0 18 21 24 25 26 27 R a R b 0 0 18 21 24 25 26 R c 0 0 0 18 21 24 25 Example Using Registers: Temperature Display • Use three 5-bit registers

  12. D Latch vs. D Flip-Flop • Latch is level-sensitive: Stores D when C=1 • Flip-flop is edge triggered: Stores D when C changes from 0 to 1 • Saying “level-sensitive latch,” or “edge-triggered flip-flop,” is redundant • Two types of flip-flops -- rising or falling edge triggered. • Comparing behavior of latch and flip-flop:

  13. Register Behavior

  14. Register Behavior • Sequential circuits have storage • Register: most common storage component • N-bit register stores N bits • Structure may consist of connected flip-flops I 3 I 2 I 1 I 0 reg(4) Rst Q3 Q2 Q1 Q0 3 2 1 0 I I I I 4-bit register D D D D Q Q Q Q R R R R Clk Rst Q3 Q2 Q1 Q0

  15. I3 I2 I1 I0 I: I[3] I[2] I[1] I[0] Register BehaviorVectors • Typically just describe register behaviorally • Declare output Q as reg variable to achieve storage • Uses vector types • Collection of bits • More convenient than declaring separate bits like I3, I2, I1, I0 • Vector's bits are numbered • Options: [0:3], [1:4], etc. • [3:0] • Most-significant bit is on left • Assign with binary constant (more on next slide) I 3 I 2 I 1 I 0 reg(4) Rst Q3 Q2 Q1 Q0 `timescale 1 ns/1 ns module Reg4(I, Q, Clk, Rst); input [3:0] I; output [3:0] Q; reg [3:0] Q; input Clk, Rst; always @(posedge Clk) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; end endmodule module Reg4(I3,I2,I1,I0,Q3,...); input I3, I2, I1, I0; module Reg4(I, Q, ...); input [3:0] I; vldd_ch3_Reg4.v

  16. Register BehaviorConstants • Binary constant • 4'b0000 • 4: size, in number of bits • 'b: binary base • 0000: binary value • Other constant bases possible • d: decimal base, o: octal base, h: hexadecimal base • 12'hFA2 • 'h: hexadecimal base • 12: 3 hex digits require 12 bits • FA2: hex value • Size is always in bits, and optional • 'hFA2 is OK • For decimal constant, size and 'd optional • 8'd255 or just 255 • In previous uses like “A <= 1;” 1 and 0 are actually decimal numbers. ‘b1 and ‘b0 would explicitly represent bits • Underscores may be inserted into value for readability • 12'b1111_1010_0010 • 8_000_000 I 3 I 2 I 1 I 0 reg(4) Rst Q3 Q2 Q1 Q0 `timescale 1 ns/1 ns module Reg4(I, Q, Clk, Rst); input [3:0] I; output [3:0] Q; reg [3:0] Q; input Clk, Rst; always @(posedge Clk) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; end endmodule vldd_ch3_Reg4.v

  17. Register Behavior • Procedure's event control involves Clk input • Not the I input. Thus, synchronous • "posedge Clk" • Event is not just any change on Clk, but specifically change from 0 to 1 (positive edge) • negedge also possible • Process has synchronous reset • Resets output Q only on rising edge of Clk • Process writes output Q • Q declared as reg variable, thus stores value too I 3 I 2 I 1 I 0 reg(4) Rst Q3 Q2 Q1 Q0 `timescale 1 ns/1 ns module Reg4(I, Q, Clk, Rst); input [3:0] I; output [3:0] Q; reg [3:0] Q; input Clk, Rst; always @(posedge Clk) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; end endmodule vldd_ch3_Reg4.v

  18. `timescale 1 ns/1 ns module Testbench(); reg [3:0] I_s; reg Clk_s, Rst_s; wire [3:0] Q_s; Reg4 CompToTest(I_s, Q_s, Clk_s, Rst_s); // Clock Procedure always begin Clk_s <= 0; #10; Clk_s <= 1; #10; end // Note: Procedure repeats // Vector Procedure initial begin Rst_s <= 1; I_s <= 4'b0000; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b0000; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1010; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1111; end endmodule Register BehaviorTestbench • reg/wire declarations and module instantiation similar to previous testbenches • Module uses two procedures • One generates 20 ns clock • 0 for 10 ns, 1 for 10 ns • Note: always procedure repeats • Other provides values for inputs Rst and I (i.e., vectors) • initial procedure executes just once, does not repeat • (more on next slide) vldd_ch3_Reg4TB.v

  19. `timescale 1 ns/1 ns module Testbench(); reg [3:0] I_s; reg Clk_s, Rst_s; wire [3:0] Q_s; Reg4 CompToTest(I_s, Q_s, Clk_s, Rst_s); // Clock Procedure always begin Clk_s <= 0; #10; Clk_s <= 1; #10; end // Note: Procedure repeats // Vector Procedure initial begin Rst_s <= 1; I_s <= 4'b0000; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b0000; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1010; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1111; end endmodule Register BehaviorTestbench • Variables/nets can be shared between procedures • Only one procedure should write to variable • Variable can be read by many procedures • Clock procedure writes to Clk_s • Vector procedures reads Clk_s • Event control "@(posedge Clk_s)" • May be prepended to statement to synchronize execution with event occurrence • Statement may be just ";" as in example • In previous examples, the “statement” was a sequential block (begin-end) • Test vectors thus don't include the clock's period hard coded • Care taken to change input values away from clock edges vldd_ch3_Reg4TB.v

  20. Clk_s Rst_s 0000 1010 1111 I_s xxxx 0000 1010 1111 Q_s 40 60 70 80 10 20 30 50 time (ns) Register BehaviorTestbench ... // Vector Procedure initial begin Rst_s <= 1; I_s <= 4'b0000; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b0000; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1010; @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1111; end • Simulation results • Note that Q_s updated only on rising clock edges • Note Q_s thus unknown until first clock edge • Q_s is reset to “0000” on first clock edge vldd_ch3_Reg4TB.v ... always @(posedge Clk) begin if (Rst == 1 ) Q <= 4'b0000; else Q <= I; end ... Remember that Q_s is connected to Q, and I_s to I, in the testbench vldd_ch3_Reg4.v Initial value of a bit is the unknown value x

  21. Clk_s Rst_s I_s Q_s 40 60 70 80 10 20 30 50 time (ns) Common Pitfalls // Vector Procedure always begin Rst_s <= 1; I_s <= 4'b0000; @(posedge Clk_s); ... @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1111; end • Using "always" instead of "initial" procedure • Causes repeated procedure execution • Not including any delay control or event control in an always procedure • May cause infinite loop in the simulator • Simulator executes those statements over and over, never executing statements of another procedure • Simulation time can never advance • Symptom – Simulator appears to just hang, generating no waveforms // Vector Procedure always begin Rst_s <= 1; I_s <= 4'b0000; end

  22. Common Pitfalls • Not initializing all module inputs • May cause undefined outputs • Or simulator may initialize to default value. Switching simulators may cause design to fail. • Tip: Immediately initialize all module inputs when first writing procedure // Vector Procedure always begin Rst_s <= 1; I_s <= 4'b0000; @(posedge Clk_s); ... @(posedge Clk_s); #5 Rst_s <= 0; I_s <= 4'b1111; end

  23. Common Pitfalls • Forgetting to explicitly declare as a wire an indentifier used in a port connection • e.g., Q_s • Verilog implicitly declares identifier as a net of the default net type, typically a one-bit wire • Intended as shortcut to save typing for large circuits • May not give warning message during compilation • Works fine if a one-bit wire was desired • But may be mismatch – in this example, the wire should have been four bits, not one bit • Unexpected simulation results • Always explicitly declare wires • Best to avoid use of Verilog's implicit declaration shortcut `timescale 1 ns/1 ns module Testbench(); reg [3:0] I_s; reg Clk_s, Rst_s; wire [3:0] Q_s; Reg4 CompToTest(I_s, Q_s, Clk_s, Rst_s); ...

  24. Finite-State Machines (FSMs)—Sequential Behavior

  25. b Controller laser x clk patient 3.3 Finite-State Machines (FSMs) and Controllers • Want sequential circuit with particular behavior over time • Example: Laser timer • Push button: x=1 for 3 clock cycles • How? Let’s try three flip-flops • b=1 gets stored in first D flip-flop • Then 2nd flip-flop on next cycle, then 3rd flip-flop on next • OR the three flip-flop outputs, so x should be 1 for three cycles

  26. Need a Better Way to Design Sequential Circuits • Trial and error is not a good design method • Will we be able to “guess” a circuit that works for other desired behavior? • How about counting up from 1 to 9? Pulsing an output for 1 cycle every 10 cycles? Detecting the sequence 1 3 5 in binary on a 3-bit input? • And, a circuit built by guessing may have undesired behavior • Laser timer: What if press button again while x=1? x then stays one another 3 cycles. Is that what we want? • Combinational circuit design process had two important things • A formal way to describe desired circuit behavior • Boolean equation, or truth table • A well-defined process to convert that behavior to a circuit • We need those things for sequence circuit design

  27. Outputs: x clk ^ x=0 x=1 O ff On clk ^ Describing Behavior of Sequential Circuit: FSM • Finite-State Machine (FSM) • A way to describe desired behavior of sequential circuit • Akin to Boolean equations for combinational behavior • List states, and transitions among states • Example: Make x change toggle (0 to 1, or 1 to 0) every clock cycle • Two states: “Off” (x=0), and “On” (x=1) • Transition from Off to On, or On to Off, on rising clock edge • Arrow with no starting state points to initial state (when circuit first starts)

  28. Outputs: x clk ^ clk ^ clk ^ x=0 x=1 x=1 x=1 O ff On1 On2 On3 clk ^ clk O ff On1 On2 On3 O ff On1 On2 On3 O ff State Outputs: x FSM Example: 0,1,1,1,repeat • Want 0, 1, 1, 1, 0, 1, 1, 1, ... • Each value for one clock cycle • Can describe as FSM • Four states • Transition on rising clock edge to next state

  29. Inputs: b; Outputs: x x=0 clk ^ O ff ^ b ’*clk b*clk ^ clk clk ^ ^ x=1 x=1 x=1 On1 On2 On3 Extend FSM to Three-Cycles High Laser Timer • Four states • Wait in “Off” state while b is 0 (b’) • When b is 1 (and rising clock edge), transition to On1 • Sets x=1 • On next two clock edges, transition to On2, then On3, which also set x=1 • So x=1 for three cycles after button pressed

  30. Inputs: b; Outputs: x x=0 clk ^ O ff ^ b’ *clk b *clk ^ clk clk ^ ^ x=1 x=1 x=1 On1 On2 On3 Inputs: b; Outputs: x x=0 Off b ’ b x=1 x=1 x=1 On1 On2 On3 FSM Simplification: Rising Clock Edges Implicit • Showing rising clock on every transition: cluttered • Make implicit -- assume every edge has rising clock, even if not shown • What if we wanted a transition without a rising edge • We don’t consider such asynchronous FSMs -- less common, and advanced topic • Only consider synchronous FSMs -- rising edge on every transition a Note: Transition with no associated condition thus transistions to next state on next clock cycle

  31. Inputs: b; Outputs: x x=0 Off b ’ b x=1 x=1 x=1 On1 On2 On3 FSM Definition • FSM consists of • Set of states • Ex: {Off, On1, On2, On3} • Set of inputs, set of outputs • Ex: Inputs: {x}, Outputs: {b} • Initial state • Ex: “Off” • Set of transitions • Describes next states • Ex: Has 5 transitions • Set of actions • Sets outputs while in states • Ex: x=0, x=1, x=1, and x=1 We often draw FSM graphically, known as state diagram Can also use table (state table), or textual languages

  32. Inputs: b; Outputs: x x=0 Off b ’ b x=1 x=1 x=1 On1 On2 On3 outputs FSM inputs x FSM b FSM outputs Combinational logic n1 FSM inputs O I FSM outputs n0 Combinational logic s1 s0 S State register clk m m m-bit state register clk N General version Standard Controller Architecture • How implement FSM as sequential circuit? • Use standard architecture • State register -- to store the present state • Combinational logic -- to compute outputs, and next state • For laser timer FSM • 2-bit state register, can represent four states • Input b, output x • Known as controller a

  33. Finite-State Machines (FSMs)—Sequential Behavior • Finite-state machine (FSM) is a common model of sequential behavior • Example: If B=1, hold X=1 for 3 clock cycles • Note: Transitions implicitly ANDed with rising clock edge • Implementation model has two parts: • State register • Combinational logic • HDL model will reflect those two parts Inputs: B; Outputs: X X=0 Off B B X=1 X=1 X=1 On1 On2 On3 FSM inputs X B FSM outputs Combinational logic State State register Clk StateNext

  34. Inputs: B; Outputs: X X=0 Off B B X=1 X=1 X=1 On1 On2 On3 FSM inputs X B FSM outputs Combinational logic State State register Clk StateNext Finite-State Machines (FSMs)—Sequential BehaviorModules with Multiple Procedures and Shared Variables • Code will be explained on following slides ... S_On1: begin X <= 1; StateNext <= S_On2; end S_On2: begin X <= 1; StateNext <= S_On3; end S_On3: begin X <= 1; StateNext <= S_Off; end endcase end // StateReg always @(posedge Clk) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; end endmodule `timescale 1 ns/1 ns module LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 0, S_On1 = 1, S_On2 = 2, S_On3 = 3; reg [1:0] State, StateNext; // CombLogic always @(State, B) begin case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end ... vldd_ch3_LaserTimerBeh.v

  35. Finite-State Machines (FSMs)—Sequential Behavior • Modules has two procedures • One procedure for combinational logic • One procedure for state register • But it's still a behavioral description `timescale 1 ns/1 ns module LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 0, S_On1 = 1, S_On2 = 2, S_On3 = 3; reg [1:0] State, StateNext; // CombLogic always @(State, B) begin ... end // StateReg always @(posedge Clk) begin ... end endmodule FSM inputs X B FSM outputs Combinational logic State State register Clk StateNext vldd_ch3_LaserTimerBeh.v

  36. Finite-State Machines (FSMs)—Sequential BehaviorParameters • parameter declaration • Not a variable or net, but rather a constant • A constant is a value that must be initialized, and that cannot be changed within the module’s definition • Four parameters defined • S_Off, S_On1, S_On2, S_On3 • Correspond to FSM’s states • Should be initialized to unique values `timescale 1 ns/1 ns module LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 0, S_On1 = 1, S_On2 = 2, S_On3 = 3; reg [1:0] State, StateNext; // CombLogic always @(State, B) begin ... end // StateReg always @(posedge Clk) begin ... end endmodule vldd_ch3_LaserTimerBeh.v

  37. FSM inputs X B FSM outputs Combinational logic State State register Clk StateNext Finite-State Machines (FSMs)—Sequential Behavior • Module declares two reg variables • State, StateNext • Each is 2-bit vector (need two bits to represent four unique state values 0 to 3) • Variables are shared between CombLogic and StateReg procedures • CombLogic procedure • Event control sensitive to State and input B • Will output StateNext and X • StateReg procedure • Sensitive to Clk input • Will output State, which it stores `timescale 1 ns/1 ns module LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 0, S_On1 = 1, S_On2 = 2, S_On3 = 3; reg [1:0] State, StateNext; // CombLogic always @(State, B) begin ... end // StateReg always @(posedge Clk) begin ... end endmodule vldd_ch3_LaserTimerBeh.v

  38. Finite-State Machines (FSMs)—Sequential BehaviorProcedures with Case Statements • Procedure may use case statement • Preferred over if-else-if when just one expression determines which statement to execute • case (expression) • Execute statement whose case item expression value matches case expression • case item expression : statement • statement is commonly a begin-end block, as in example • First case item expression that matches executes; remaining case items ignored • If no item matches, nothing executes • Last item may be "default :statement" • Statement executes if none of the previous items matched // CombLogic always @(State, B) begin case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end S_On1: begin X <= 1; StateNext <= S_On2; end S_On2: begin X <= 1; StateNext <= S_On3; end S_On3: begin X <= 1; StateNext <= S_Off; end endcase end vldd_ch3_LaserTimerBeh.v

  39. Inputs: X; Outputs: B X=0 Off B' B X=1 X=1 X=1 On1 On2 On3 Finite-State Machines (FSMs)—Sequential BehaviorProcedures with Case Statements • FSM’s CombLogic procedure • Case statement describes states • case (State) • Executes corresponding statement (often a begin-end block) based on State's current value • A state's statements consist of • Actions of the state • Setting of next state (transitions) • Ex: State is S_On1 • Executes statements for state On1, jumps to endcase reg [1:0] State, StateNext; // CombLogic always @(State, B) begin case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end S_On1: begin X <= 1; StateNext <= S_On2; end S_On2: begin X <= 1; StateNext <= S_On3; end S_On3: begin X <= 1; StateNext <= S_Off; end endcase end Suppose State is S_On1 vldd_ch3_LaserTimerBeh.v

  40. Finite-State Machines (FSMs)—Sequential Behavior • FSM StateReg Procedure • Similar to 4-bit register • Register for State is 2-bit vector reg variable • Procedure has synchronous reset • Resets State to FSM’s initial state, S_Off ... parameter S_Off = 0, S_On1 = 1, S_On2 = 2, S_On3 = 3; reg [1:0] State, StateNext; ... // StateReg always @(posedge Clk) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; end ... vldd_ch3_LaserTimerBeh.v

  41. Inputs: B; Outputs: X X=0 Off B B X=1 X=1 X=1 On1 On2 On3 FSM inputs X B FSM outputs Combinational logic State State register Clk StateNext Finite-State Machines (FSMs)—Sequential BehaviorModules with Multiple Procedures and Shared Variables • Code should now be clear ... S_On1: begin X <= 1; StateNext <= S_On2; end S_On2: begin X <= 1; StateNext <= S_On3; end S_On3: begin X <= 1; StateNext <= S_Off; end endcase end // StateReg always @(posedge Clk) begin if (Rst == 1 ) State <= S_Off; else State <= StateNext; end endmodule `timescale 1 ns/1 ns module LaserTimer(B, X, Clk, Rst); input B; output reg X; input Clk, Rst; parameter S_Off = 0, S_On1 = 1, S_On2 = 2, S_On3 = 3; reg [1:0] State, StateNext; // CombLogic always @(State, B) begin case (State) S_Off: begin X <= 0; if (B == 0) StateNext <= S_Off; else StateNext <= S_On1; end ... vldd_ch3_LaserTimerBeh.v

  42. Clk_s Rst_s B_s X_s 40 60 70 80 10 20 30 50 90 100 110 time (ns) Finite-State Machines (FSMs)—Sequential BehaviorSelf-Checking Testbenches ... // Clock Procedure always begin Clk_s <= 0; #10; Clk_s <= 1; #10; end // Note: Procedure repeats // Vector Procedure initial begin Rst_s <= 1; B_s <= 0; @(posedge Clk_s); #5 Rst_s <= 0; @(posedge Clk_s); #5 B_s <= 1; @(posedge Clk_s); #5 B_s <= 0; @(posedge Clk_s); @(posedge Clk_s); @(posedge Clk_s); end endmodule • FSM testbench • First part of file (variable/net declarations, module instantiations) similar to before • Vector Procedure • Resets FSM • Sets FSM's input values (“test vectors”) • Waits for specific clock cycles • We observe the resulting waveforms to determine if FSM behaves correctly vldd_ch3_LaserTimerTB.v

  43. Finite-State Machines (FSMs)—Sequential BehaviorSelf-Checking Testbenches • Reading waveforms is error-prone • Create self-checking testbench • Useif statements to check for expected values • If a check fails, print error message • Ex: if X_s fell to 0 one cycle too early, simulation might output: • 95: Third X=1 failed // Vector Procedure initial begin Rst_s <= 1; B_s <= 0; @(posedge Clk_s); #5 if (X_s != 0) $display("%t: Reset failed", $time); Rst_s <= 0; @(posedge Clk_s); #5 B_s <= 1; @(posedge Clk_s); #5 B_s <= 0; if (X_s != 1) $display("%t: First X=1 failed", $time); @(posedge Clk_s); #5 if (X_s != 1) $display("%t: Second X=1 failed", $time); @(posedge Clk_s); #5 if (X_s != 1) $display("%t: Third X=1 failed", $time); @(posedge Clk_s); #5 if (X_s != 0) $display("%t: Final X=0 failed", $time); end Clk_s Rst_s B_s X_s 40 60 70 80 10 20 30 50 90 100 110 time (ns) vldd_ch3_LaserTimerTBDisplay.v

  44. Finite-State Machines (FSMs)—Sequential Behavior$display System Procedure • $display – built-in Verilog system procedure for printing information to display during simulation • A system procedure interacts with the simulator and/or host computer system • To write to a display, read a file, get the current simulation time, etc. • Starts with $ to distinguish from regular procedures • String argument is printed literally... • $display("Hello") will print "Hello" • Automatically adds newline character • ...except when special sequences appear • %t: Display a time expression • Time expression must be next argument • $time – Built-in system procedure that returns the current simulation time • 95: Third X=1 failed // Vector Procedure initial begin Rst_s <= 1; B_s <= 0; @(posedge Clk_s); #5 if (X_s != 0) $display("%t: Reset failed", $time); Rst_s <= 0; @(posedge Clk_s); #5 B_s <= 1; @(posedge Clk_s); #5 B_s <= 0; if (X_s != 1) $display("%t: First X=1 failed", $time); @(posedge Clk_s); #5 if (X_s != 1) $display("%t: Second X=1 failed", $time); @(posedge Clk_s); #5 if (X_s != 1) $display("%t: Third X=1 failed", $time); @(posedge Clk_s); #5 if (X_s != 0) $display("%t: Final X=0 failed", $time); end vldd_ch3_LaserTimerTBDisplay.v

  45. Controller Example: Button Press Synchronizer • Want simple sequential circuit that converts button press to single cycle duration, regardless of length of time that button actually pressed • We assumed such an ideal button press signal in earlier example, like the button in the laser timer controller Button press synchronizer controller bi bo

  46. Step 2: Create architecture bi bo FSM outputs FSM inputs FSM inputs: bi; FSM outputs: bo Combinational logic bi ’ n1 bi b i ’ n0 bi ’ C A B s1 s0 bi bi n1 = s1’s0bi + s1s0bi n0 = s1’s0’bi bo = s1’s0bi’ + s1’s0bi = s1s0 State register bo=0 bo=1 bo=0 clk Step 1: FSM Combinational logic outputs bo bi n1 FSM inputs: bi; FSM outputs: bo bi ’ bi n0 bi ’ bi ’ 10 00 01 bi bi bo=0 bo=1 bo=0 s1 s0 Step 3: Encode states State register clk Step 4: State table Step 5: Create combinational circuit Controller Example: Button Press Synchronizer (cont) a FSM Step 5: Create combinational circuit

  47. w Inputs: none; Outputs: w,x,y,z Inputs: none; Outputs: w,x,y,z x y wxyz=0001 wxyz=1000 wxyz=0001 wxyz=1000 Combinational logic z A D A D n1 00 11 n0 s1 s0 01 10 State register B C B C clk wxyz=0011 wxyz=1100 wxyz=0011 wxyz=1100 Step 2: Create architecture Step 1: Create FSM Step 3: Encode states w FSM outputs x y z n0 n1 s1 s0 State register clk Step 4: Create state table Controller Example: Sequence Generator • Want generate sequence 0001, 0011, 1100, 1000, (repeat) • Each value for one clock cycle • Common, e.g., to create pattern in 4 lights, or control magnets of a “stepper motor” w = s1 x = s1s0’ y = s1’s0 z = s1’ n1 = s1 xor s0 n0 = s0’ a Step 5: Create combinational circuit

  48. w Inputs: none; Outputs: w,x,y,z Inputs: none; Outputs: w,x,y,z x y wxyz=0001 wxyz=1000 wxyz=0001 wxyz=1000 Combinational logic z A D A D n1 00 11 n0 s1 s0 01 10 State register B C B C clk wxyz=0011 wxyz=1100 wxyz=0011 wxyz=1100 Step 2: Create architecture Step 1: Create FSM Step 3: Encode states w FSM outputs x y z n0 n1 s1 s0 State register clk Step 4: Create state table Controller Example: Sequence Generator • Want generate sequence 0001, 0011, 1100, 1000, (repeat) • Each value for one clock cycle • Common, e.g., to create pattern in 4 lights, or control magnets of a “stepper motor” w = s1 x = s1s0’ y = s1’s0 z = s1’ n1 = s1 xor s0 n0 = s0’ a Step 5: Create combinational circuit

  49. I nputs: a ; O utputs: r W ait r=0 a ’ a K1 K2 K3 K4 r=1 r=1 r=0 r=1 clk I nputs a clk I nputs State W ait W ait K1 K2 K3 K4 W ait a S t a t e W ait W ait K1 K2 K3 K4 W ait W ait Output r O utputs r FSM Example: Secure Car Key (cont.) • Nice feature of FSM • Can evaluate output behavior for different input sequence • Timing diagrams show states and output values for different input waveforms Q: Determine states and r value for given input waveform: K1 a

  50. I nputs: a ; O utputs: r Inputs: a; Outputs: r 000 Wait a ’ r=0 r=0 a ’ a a Step 1 K1 K2 K3 K4 100 001 010 011 r=1 r=1 r=0 r=1 r=1 r=1 r=0 r=1 outputs a r Combinational logic FSM n2 inputs Step 2 n1 n0 s2 s1 s0 State register clk Step 3 Step 4 Controller Example: Secure Car Key • (from earlier example) a FSM We’ll omit Step 5

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