SEE and TID Extension Testing of the Xilinx XQR18V04 4Mbit Radiation Hardened Configuration PROM

1. SEE and TID Extension Testing of the Xilinx XQR18V04 4Mbit Radiation Hardened Configuration PROM Authors Carl Camichael (Xilinx, Inc.) Joe Fabula (Xilinx, Inc.) Gary Swift (Jet Propulsion Laboratory) Steve Guertin (Jet Propulsion Laboratory) Candice Yui (Jet Propulsion Laboratory)

2. Abstract The XQR18V04 was evaluated for single event upset rates using Proton and Heavy Ion. The PROM was demonstrated to be immune to latch-up, as well as to static upset in the flash memory cells, to an LET > 125 MeV/mg/cm2 (effective). The PROM was also tested in a dynamic mode, which revealed three distinct error modes: Read Bit Errors, Address Errors, and a Single Event Functional Interrupt (SEFI) which effected the data output drivers. Saturation cross-sections and onset thresholds for these error modes were measured at the heavy ion facility at Texas A&M University, and the proton facility at UC Davis. Additional testing was performed at UC Davis and the Cobalt 60 source at McClellan Air Force Base to examine the effect to TID life as a function of power biasing. The PROM demonstrated a 100% improvement in total TID life from an 84% percent decrease in device usage.

3. XQR18V04 SEU & TID Experiments • Heavy Ion • Cyclotron at Texas A&M University • Static & Latch-up testing 4-20-2001 • Dynamic Error and SEFI testing 3-20-2002 • Proton • Cyclotron at UC Davis • Dynamic Error, SEFI, and TID testing 3-7-2002 • Gamma • Cobalt 60 Source, Mclellan Air Force Base • TID extension testing 12-4-2001

4. XQR18V04 Internal Architecture TDI Control and JTAG Interface D0/DATA TCK D1 TMS Serial or Parallel Output Interface D2 Flash Memory D3 TDO D4 CF D5 D6 D7 CE Address Counter CEO OE/RST

5. XQR18V04 Heavy Ion Static SEU & Latch-up Testing • Pre-programmed DUT exposed to Au ion beam at LET of 83 and 119 MeV/mg/cm2.. • Post-beam JTAG read out verified data retention and no static errors. • Re-programmability of DUT verified post Latch Test.

6. XQR18V04 SEU Dynamic Test Methodology • Simultaneous Read of DUT and Comparison (Gold) Chip • Test Control Device: XCV300 PQ240 • Reset Devices • Compare bit-by-bit Data Output • Compare CEO transitions • Track Error Signatures: • Bit Errors • Address Errors • CEO Errors • Stuck Outputs • SEFIs (other error)

7. XQR18V04 SEU Dynamic Test Board

8. XQR18V04 SEU Dynamic Test Architecture 8 Bit Parallel Interface XQR18V04 PC44 GOLD Dell Laptop XCV300 PQ240 PC FPGA XQR18V04 PC44 Control Panel JTAG ChipScope Software DUT LPT1 Parallel Cable III 8 Bit Parallel Interface

9. FPGA Control Chip Architecture Test Runs Counter 32 ILA6 Bit Errors Counter 32 Gold Chip I/O Interface ILA0 Address Error Counter 32 ILA1 Finite State Machine CEO Error Counter 32 ILA2 Stuck @ 0 Counter 32 ILA3 DUT Chip I/O Interface Stuck @ 1 Counter 32 ILA4 Pwr Cyc/Run Errors Counter 32 ILA5 JTAG ICON

10. Dynamic Test: Error Definitions • Bit Errors (Transient Data Read): • Differences in the data output of the two proms, but the CEOs are synchronous. • Address Errors (SEFI): • Differences in the data output of the two proms, and the CEOs are not synchronous. • CEO Errors • No Differences in the data output of the two proms, but the CEOs are not synchronous. • Stuck @ 1 or 0 • Flow1 (nc): DUT data outputs do not transition. • Flow1 (nc2): DUT data outputs do not transition after first bit error.

11. SEE Test Flow 1 - Continuous Cycle Initialize Test Enable Devices START SWITCH Run Test NO CEO=0 ? Reset Devices YES End Test Power Up Check Data Power Down 0 YES 1 Stuck Bits ? Stuck Runs? NO 2 Update Data

12. Heavy Ion Testing (Dynamic) Species and Energy Spectrum

13. Transient Data Read Errors Weibull Parameters Limit = 4.46E-5 cm2 L0 = 11.0 w = 3 s = 2

14. Address SEFI Errors Weibull Parameters Limit = 2.09E-4 cm2 L0 = 1.0 w = 18 s = 2

15. SEFI: Output Driver Enable Weibull Parameters Limit = 2.4E-6 cm2 L0 = 11.6 w = 2 s = 2

16. XQR18V04 Heavy Ion Dynamic Test Analysis • No CEO Errors observed. • No Stuck @ (0 or 1) conditions were observed. • Additional SEFI observed: • Parallel Data Output Driver Disabled. • Recovered by Logical Reset of DUT.

17. Proton Dynamic Test:Read & Address Upsets (With Power Cycling)

18. Extending TID of the XQR18V04 with Power Duty Cycle • 40krad(Si) nominal Total Ionizing Dose Limit (100% Bias). • Mil Std 883 Method 1019.5 • Un-powered Gamma Dose Limit Test • Attached GND, No VCC, Active Clock. • 100krad(Si) Fully functional after test. • 300krad(Si) Fully functional after 168 hours unbiased anneal. • Power Cycling Proton Dose Test • First functional failure between 80~100 krad(Si) using 16% power duty cycle. • TIDEffective = 40E3*(2((2-log(PON))) if < 300krad

19. Extending TID Life with Power Cycling Gamma Test Limit (300krad) Proton Measurements Theoretical Curve

20. Example Calculation of effective PROM TID Life per Application/Orbit TIDEffective = 40E3*(2((2-log(PON))) if < 300krad • Power PROM for Each Scrub Cycle • Scrub Cycle = FPGA configuration bits / 8 / CCLK Frequency. • FPGA (V300) = 1.5E6 bits, CCLK = 11MHz: • Scrub Cycle = 17 ms. • Prom utilization 100,000 scrub cycles per FPGA bit error. • V300, 1000km @ 60 degrees: Upset rate = 1 bit per day per device. • PROM ON Time = 100000 x 17ms = 1700 s. • PON(%) = (170/ 86,400) x 100% = 01.97 % • TIDEffective = 40E3*(2((2-log(PON))) = 130 krad.