Lecture 18: Input/Output (I/O): Buses and Peripherals

1. Lecture 18:Input/Output (I/O):Buses and Peripherals Michael B. Greenwald Computer Architecture CIS 501 Fall 1999

2. I/O Systems interrupts Processor Cache Memory - I/O Bus Main Memory I/O Controller I/O Controller I/O Controller Graphics Disk Disk Network Time(workload) = Time(CPU) + Time(I/O) - Time(Overlap)

3. Motivation: Who Cares About I/O? • CPU Performance: 50% to 100% per year • Multiprocessor supercomputers 150% per year • I/O system performance limited by mechanical delays < 5% per year (IO per sec or MB per sec) • Amdahl's Law: system speed-up limited by the slowest part! 10% IO & 10x CPU => 5x Performance (lose 50%) 10% IO & 100x CPU => 10x Performance (lose 90%) • I/O bottleneck: Diminishing fraction of time in CPU Diminishing value of faster CPUs

4. Bus-Based Interconnect • Bus: a shared communication path between subsystems • Low cost: a single set of wires is shared multiple ways • Versatility: Easy to add new devices & peripherals may even be ported between computers using common bus (standardization) • Disadvantage • A communication bottleneck, possibly limiting the maximum I/O throughput, (eventually limiting system performance) • Bus speed is limited by physical factors • the bus length • the number of devices (and, hence, bus loading). • these physical limits prevent arbitrary bus speedup.

5. Bus-Based Interconnect • Two generic types of busses: • I/O busses: lengthy, many types of devices connected, wide range in the data bandwidth, and follow a bus standard.Sometimes called a channel. • CPU–memory buses: high speed, matched to the memory system to maximize memory–CPU bandwidth, single device (actually, also a small number of devices, but known in advance!). Sometimes called a backplane. • To lower costs, low cost (older) systems combine the memory and I/O buses in one shared bus • Often, system starts with one shared bus, but memory and CPU increase in speed faster than devices do, so old memory bus becomes new I/O bus. • Bus transaction • Sending address & receiving or sending data

6. Bus Options(See Figure 6.9, page 497)

7. Example: VME bus • 3 96-pin connectors • 128 defined as standard, rest available for extension • 32 address • 32 data • 64 command & power/ground lines • IEEE 1014 is standard • Up to .5 meters • Up to 21 devices • Multiple Masters

8. Bus Options(See Figure 6.9, page 497)

9. Bus Options(See Figure 6.9, page 497) Need to understand bus transaction

10. Bus Protocols Master Slave ° ° ° Control Lines Bus Master: has ability to control the bus, initiates transaction Bus Slave: module activated by the transaction Bus Communication Protocol: specification of sequence of events and timing requirements in transferring information. Asynchronous Bus Transfers: control lines (req., ack.) serve to orchestrate sequencing Synchronous Bus Transfers: sequence relative to common clock Address Lines Data Lines

11. Synchronous Bus Protocols Master Clock Address Data Read Wait Read complete Slave begin read Pipelined/Split transaction Bus Protocol (a.k.a. packet-switched bus) Address Data Wait addr 1 addr 2 addr 3 data 0 data 1 data 2 wait 1 OK 1

12. Asynchronous HandshakeWrite Transaction Address Data Read Req. Ack. Master Asserts Address Next Address t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target\ t1: Master asserts request line t2: Slave asserts ack, indicating data received t3: Master releases req t4: Slave releases ack Master Asserts Data 4 Cycle Handshake t0 t1 t2 t3 t4 t5

13. Asynchronous HandshakeRead Transaction Address Data Read Req Ack Master Asserts Address Next Address t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target\ t1: Master asserts request line t2: Slave asserts ack, indicating ready to transmit data t3: Master releases req, data received t4: Slave releases ack 4 Cycle Handshake t0 t1 t2 t3 t4 t5 Time Multiplexed Bus: address and data share lines

14. Time Multiplexed Bus • Definition: address and data share lines, fewer lines • Cheaper • Slower • More complex protocols • Need some way of distinguishing between addr and data, start and end of xaction. • In-band: delimiters, tokens, header/trailer • Out-of-band: control lines.

15. Bus Arbitration Parallel (Centralized) Arbitration Serial Arbitration: (logical) daisy chaining,fixed priority Polling Bus Request Bus Grant BR BG BR BG BR BG M M M BG BR BGi BGo BGi BGo BGi BGo M M M A.U. BR BR BR M M M A.U. BR A C BR A C BR A C BR A

16. Processor Interface IssuesHow does bus interface with/to processor? • Interconnections/Buses • Shared vs. separate Memory/IO buses • Attach to memory, cache, or proc.(separate only) • Processor communication interface • I/O interface vs. Memory mapped I/O • I/O Control Structure • Polling • Interrupts • DMA • I/O Controllers • I/O Processors

17. Shared Bus interrupts Processor Cache Memory - I/O Bus Main Memory I/O Controller I/O Controller I/O Controller Graphics Disk Disk Network Time(workload) = Time(CPU) + Time(I/O) - Time(Overlap)

18. Separate Buses Memory Bus Cache Bus Adaptor Main Memory interrupts Processor I/O Bus I/O Controller I/O Controller I/O Controller Graphics Disk Disk Network Time(workload) = Time(CPU) + Time(I/O) - Time(Overlap)(More overlap between I/O and Memory buses).

19. Processor Interface IssuesHow does bus interface with/to processor? • Interconnections/Buses • Shared vs. separate Memory/IO buses • Attach to memory, cache, or proc.(separate only) • Processor communication interface • I/O interface vs. Memory mapped I/O • I/O Control Structure • Polling • Interrupts • DMA • I/O Controllers • I/O Processors

20. Connection point: memory Memory Bus Cache Bus Adaptor Main Memory interrupts Processor I/O Bus I/O Controller I/O Controller I/O Controller Graphics Disk Disk Network Stale data, consistency traffic.

21. Connection point: cache Memory Bus Cache Bus Adaptor Main Memory interrupts Processor I/O Bus I/O Controller I/O Controller I/O Controller Graphics Disk Disk Network No Stale data, but lost performance because of cache pollution and arbitration between I/O and CPU on cache access (increase hit time/cycle time?)

22. Processor Interface IssuesHow does bus interface with/to processor? • Interconnections/Buses • Shared vs. separate Memory/IO buses • Attach to memory, cache, or proc.(separate only) • Processor communication interface • I/O interface vs. Memory mapped I/O • I/O Control Structure • Polling • Interrupts • DMA • I/O Controllers • I/O Processors

23. How does processor access I/O devices? • Need to read and write control and status registers. • Need to transfer data to/from I/O device

24. I/O Interface CPU Memory memory bus Independent I/O Bus Seperate I/O instructions (in,out) Interface Interface Peripheral Peripheral CPU Lines distinguish between I/O and memory transfers common memory & I/O bus 40 Mbytes/sec optimistically 10 MIP processor completely saturates the bus! VME bus Multibus-II Nubus Memory Interface Interface Peripheral Peripheral

25. Memory Mapped I/O CPU Single Memory & I/O Bus No Separate I/O Instructions ROM RAM Memory Interface Interface Peripheral Peripheral CPU $ I/O L2 $ Bus Adaptor snoops memory bus transactions and converts I/O space addresses to I/O operations on I/O bus. (converts I/O ops to memory reads and writes, too). Memory Bus I/O bus Memory Bus Adaptor

26. I/O Architecture • Hardware covers interconnection point and number of buses. • Software architecture: how I/O is managed by processor(s).