1 / 91

未经作者允许，请勿发布该文档！ yingqichen@sjtu

未经作者允许，请勿发布该文档！ yingqichen@sjtu.edu.cn. VHDL. Synthesis & Simulation (Basic Language Items). Agenda. Overview Entity Architecture Library & Use Package Configuration. Include… Entity Architecture. Basic Language Framework. library ieee; use ieee.std_logic_1164.all;

tamal
Download Presentation

未经作者允许，请勿发布该文档！ yingqichen@sjtu

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. 未经作者允许，请勿发布该文档！yingqichen@sjtu.edu.cn未经作者允许，请勿发布该文档！yingqichen@sjtu.edu.cn

  2. VHDL Synthesis & Simulation (Basic Language Items)

  3. Agenda • Overview • Entity • Architecture • Library & Use • Package • Configuration

  4. Include… Entity Architecture Basic Language Framework library ieee; use ieee.std_logic_1164.all; --------------------------------------------- entity XYZ is port ( A, B, C : in std_logic; -- Comments F : out std_logic ); end XYZ; --------------------------------------------- architecture XYZ_arch of XYZ is begin F <= (A and B) or (B and C) or (C and A); end XYZ_arch;

  5. Agenda • Overview • Entity • Keywords • Port • Generic • Architecture • Library & Use • Package • Configuration

  6. Include… Entity Architecture Entity library ieee; use ieee.std_logic_1164.all; --------------------------------------------- entity XYZ is port ( A, B, C : in std_logic; F : out std_logic ); end XYZ; --------------------------------------------- architecture XYZ_arch of XYZ is begin F <= (A and B) or (B and C) or (C and A); end XYZ_arch;

  7. Entity Definition entityentity_name is [Generics;] [Ports;] [Other Declarative Parts;] [Statements;] end[ entity][ entity_name ] ;

  8. ROM Entity Examples (ROM) entityROM is port ( D0 : out bit; D1 : out bit; D2 : out bit; D3 : out bit; D4, D5, D6, D7 : out bit; A : in bit_vector(7 down to 0) ); endROM; D0D1D2D3D4D5D6D7 A0A1A2A3A4A5A6A7

  9. Entity Examples (Adder) entityFull_Adderis port (X, Y, Cin: in Bit; Cout, Sum: out Bit) ; endentityFull_Adder ; X Y Cin Sum Cout 

  10. Entity Examples (n-input AND) entityANDNis generic (wid : integer := 2); port ( X : in bit_vector(wid-1 downto 0); F : out bit ); end;

  11. Entity Example (Empty Entity) entityTest_Benchis endentityTest_Bench; Test_Bench Signal Generator Test Target

  12. Agenda • Overview • Entity • Keywords • Port • Generic • Architecture • Library & Use • Package • Configuration

  13. Entity Definition (Ports) entityentity_name is Generics; Ports; Other Declarative Parts; Statements; end[ entity][ entity_name ] ;

  14. Port Example (ANDN) entity ANDN is generic (wid : integer := 2); port ( X : in bit_vector(wid-1 downto 0); F : out bit ); end;

  15. A0A1A2A3A4A5A6A7 D0D1D2D3D4D5D6D7 ROM Port Examples (ROM) entity ROM is port( D0 : out bit; D1 : out bit; D2 : out bit; D3 : out bit; D4, D5, D6, D7 : out bit; A : in bit_vector(7 down to 0) ); end ROM;

  16. Port Examples (Adder) entity Full_Adder is port(X, Y, Cin: in Bit; Cout, Sum: out Bit) ; end entity Full_Adder ; X Y Cin Sum Cout 

  17. Port Examples (n-input AND) entity ANDN is generic (wid : integer := 2); port ( X : in bit_vector(wid-1 downto 0); F : out bit ); end;

  18. Port Definition Port( Port_Name[, Port_Name] : DirType[:=Default_Val]; Port_Name[, Port_Name] : DirType[:=Default_Val]; ... Port_Name[, Port_Name] : DirType[:=Default_Val]; );

  19. Each Parts of Port Port Name DirTypeDefault Value port ( A0, A1 : in std_logic; A2 :instd_logic:= ‘1’; F0 :buffer std_logic; F1 :out std_logic; F2 :inoutstd_logic );

  20. Type of “Dir” • In • Out • Inout • Buffer • Linkage

  21. Signal Direction Other IC Other IC

  22. Dir Example port ( A0, A1 : in std_logic; A2 : in std_logic := ‘1’; F0 : buffer std_logic; F1 : out std_logic; F2 : inout std_logic );

  23. Use of Dir --------------------------------- architecture ABC_arch of ABC is begin process(A0) begin if rising_edge(A0) then F0 <= not F0; F1 <= F2; end if; end process; F2 <= A1 when A2 = '1' ELSE 'Z'; end ABC_arch; library ieee; use ieee.std_logic_1164.all; ------------------------------ entity ABC is port ( A0, A1, A2 : in std_logic; F0 : buffer std_logic; F1 : out std_logic; F2 : inout std_logic ); end ABC;

  24. Type Port Name DirTypeDefault Value port ( A0, A1 : in std_logic; A2 :instd_logic:= ‘1’; F0 :buffer std_logic; F1 :out std_logic; F2 :inoutstd_logic );

  25. Typical Port Type • Bit • Bit_vector • Std_logic • Std_logic_vector

  26. Bit • ‘1’ • ‘0’

  27. X0X1X2X3 F Bit_vector Port ( X0 : in bit; X1 : in bit; X2 : in bit; X3 : in bit; F : out bit ); port ( X : in bit_vector(3 downto 0); F : out bit ); Port ( X0, X1, X2, X3 : in bit; F : out bit );

  28. ? Std_logic • 'U', -- Uninitialized • 'X', -- Forcing Unknown • '0', -- Forcing 0 • '1', -- Forcing 1 • 'Z', -- High Impedance • 'W', -- Weak Unknown • 'L', -- Weak 0 • 'H', -- Weak 1 • '-' -- Don't care

  29. 1 ? 0 Resolution Function Of Std_logic

  30. X0X1X2X3 F Std_logic_vector port ( X : in std_logic_vector(3 downto 0); F : out std_logic );

  31. Agenda • Overview • Entity • Keywords • Port • Generic • Architecture • Library & Use • Package • Configuration

  32. Entity Definition (Generics) entityentity_name is Generics; Ports; Other Declarative Parts; Statements; end[ entity][ entity_name ] ;

  33. An AND Gate With Unknown Inputs entity ANDN is generic (wid : integer := 2); port ( X : in bit_vector(wid-1 downto 0); F : out bit ); end ANDN;

  34. Generic Definition generic ( Name [, Name] : DataType[:= DefaultValue]; Name [, Name] : DataType[:= DefaultValue]; ... Name [, Name] : DataType[:= DefaultValue] );

  35. Generic Example (1) entity abcd is generic ( p_a :integer := 2; p_b :integer := 7 ); port ( A : out bit_vector(0 to p_a - 1); F : in bit ); end;

  36. Use of the Generic (ANDN.vhd) library ieee; use ieee.std_logic_1164.all; --------------------------------- entityANDNis generic (wid: integer := 2); port ( X : in bit_vector(wid-1 downto 0); F : out bit ); endANDN; --------------------------------- architecture ANDN_arch of ANDN is begin process(X) variable tmp : bit; begin tmp := '1'; for i inwid-1 downto 0 loop tmp := tmp and X(i); end loop; F <= tmp; end process; end ANDN_arch;

  37. Use of the Generic (My_package.vhd) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --------------------------------- package my_package is componentANDNis generic (wid : integer := 2); port ( X : in bit_vector(wid-1 downto 0); F : out bit ); endcomponent; end my_package;

  38. U1 A(0)A(1)A(2)A(3) F1 B(1)B(3) U2 F2 Use of the Generic (see.vhd) library ieee; use ieee.std_logic_1164.all; library work; use work.my_package.all; --------------------------------- entity SEE is port ( A : in bit_vector(3 downto 0); B : in bit_vector(1 downto 0); F1, F2 : out bit ); end SEE; --------------------------------- architecture SEE_arch of SEE is begin U1:ANDNgeneric map(4) port map (A, F1); U2: ANDN port map (B, F2); end SEE_arch;

  39. Agenda • Overview • Entity • Architecture • Keywords • Block • Process • Subprogram • Function • Procedure • Library & Use • Package • Configuration

  40. Include… Entity Architecture Architecture library ieee; use ieee.std_logic_1164.all; --------------------------------------------- entity XYZ is port ( A, B, C : in std_logic; F : out std_logic ); end XYZ; --------------------------------------------- architectureXYZ_archofXYZis begin F <= (A and B) or (B and C) or (C and A); endXYZ_arch;

  41. Architecture Definition architecturearch_nameofentity_nameis architecture_declarative_part begin architecture_statement_part end[ architecture ] [ arch_name ] ;

  42. Architecture Example (ABC.vhd) --------------------------------- architectureABC_archofABCis begin process(A0) begin if rising_edge(A0) then F0 <= not F0; F1 <= F2; end if; end process; F2 <= A1 when A2 = '1' ELSE 'Z'; endABC_arch; library ieee; use ieee.std_logic_1164.all; ------------------------------ entityABCis port( A0,A1,A2 : in std_logic; F0 : buffer std_logic; F1 : out std_logic; F2 : inout std_logic ); endABC;

  43. Architecture Example (ANDN.vhd) library ieee; use ieee.std_logic_1164.all; --------------------------------- entityANDNis generic (wid : integer := 2); port( X : in bit_vector(wid-1 downto 0); F : out bit ); endANDN; --------------------------------- architectureANDN_archofANDNis begin process(X) variable tmp : bit; begin tmp := '1'; for i in wid-1 downto 0 loop tmp := tmp and X(i); end loop; F <= tmp; end process; endANDN_arch;

  44. U1 A(0)A(1)A(2)A(3) F1 B(1)B(3) U2 F2 Use of the Generic (see.vhd) library ieee; use ieee.std_logic_1164.all; library work; use work.my_package.all; --------------------------------- entitySEEis port ( A : in bit_vector(3 downto 0); B : in bit_vector(1 downto 0); F1, F2 : out bit ); endSEE; --------------------------------- architectureSEE_archofSEEis begin U1: ANDN generic map(4) port map (A, F1); U2: ANDN port map (B, F2); endSEE_arch;

  45. Agenda • Overview • Entity • Architecture • Keywords • Block • Process • Subprogram • Function • Procedure • Library & Use • Package • Configuration

  46. Inside Architecture • How to maintain large architecture? • How to modulate the architecture code? • Separate the architecture in to several parts • How to separate the architecture? • VHDL language that can separate an architecture • Block • Process

  47. architectureblkblk_archofblkblkis signal A, B: std_logic; begin u1: block signal C, D: std_logic; begin A <= C; B <= D; C <= X; D <= X; end block u1; u2: block signal C, E: std_logic; begin C <= A; E <= B; u3: block signal E, F, G: std_logic; begin E <= A; F <= E; G <= u2.E; end block u3; end block u2; Y <= X and (A or B); endblkblk_arch; Example of Block (BLKBLK.vhd) library ieee; use ieee.std_logic_1164.all; --------------------------------- entityblkblkis port(X: in std_logic; Y: out std_logic); endblkblk;

  48. Definition of Block BlockLabel:block[( GuardExpression)][is] Declarations; begin ConcurrentStatements; end block[BlockLabel];

  49. architectureblkblk_archofblkblkis signal A, B: std_logic; begin u1: block signal C, D: std_logic; begin A <= C; B <= D; C <= X; D <= X; end block u1; u2: block signal C, E: std_logic; begin C <= A; E <= B; u3: block signal E, F, G: std_logic; begin E <= A; F <= E; G <= u2.E; end block u3; end block u2; Y <= X and (A or B); endblkblk_arch; Example of Block (BLKBLK.vhd) library ieee; use ieee.std_logic_1164.all; --------------------------------- entityblkblkis port(X: in std_logic; Y: out std_logic); endblkblk;

  50. Example of Block (Test_16.vhd) begin Blck_Test_1:block (clock = '1' and Clock'EVENT) begin Destination_1 <= guarded Source; Destination_2 <= Source; end blockBlck_Test_1; Blck_Test_2:block (Clock = '1' and not(Clock'STABLE)) begin Destination_3 <=guarded Source; Destination_4 <=Source; end blockBlck_Test_2; Monitor:process variable Source_Var : NATURAL; variable Dest_1_Var, Dest_2_Var : NATURAL; variable Dest_3_Var, Dest_4_VAr : NATURAL begin Source_Var := Source; Dest_1_Var := Destination_1; Dest_2_Var := Destination_2; Dest_3_Var := Destination_3; Dest_4_Var := Destination_4; wait on Destination_1,Destination_2, Destination_3,Destination_4; end processMonitor; Tick_Tock:process begin wait for 10 ns; Clock <=not clock; end processTick_Tock; Source_Wave: Source <=1 after 8 ns, 2 after 15 ns, 3 after 16 ns, 4 after 17 ns, 5 after 18 ns,6 after 19 ns; endBehave_1; entityTest_16 is endTest_16; architecture Behave_1ofTest_16 is signal Source : NATURAL := 0; signal Destination_1 : NATURAL := 0; signal Destination_2 : NATURAL := 0; signal Destination_3 : NATURAL := 0; signal Destination_4 : NATURAL := 0; signal Clock : BIT := '0';

More Related