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ECE 6466 “ IC Engineering ” Dr. Wanda Wosik

: Silicon VLSI Technology Fundamentals, Practice and Modeling by J. D. Plummer, M. D. Deal, and P. B. Griffin. Chapter 2 Modern CMOS Technology. ECE 6466 “ IC Engineering ” Dr. Wanda Wosik. UH; F2014. CMOS TECHNOLOGY. • We will describe a modern CMOS process flow.

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ECE 6466 “ IC Engineering ” Dr. Wanda Wosik

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  1. :Silicon VLSI TechnologyFundamentals, Practice and Modelingby J. D. Plummer, M. D. Deal, and P. B. Griffin Chapter 2 Modern CMOS Technology ECE 6466 “IC Engineering” Dr. Wanda Wosik UH; F2014

  2. CMOS TECHNOLOGY • We will describe a modern CMOS process flow. • In the simplest CMOS technologies, we need to realize simply NMOS and PMOS transistors for circuits like those illustrated below. • Typical CMOS technologies in manufacturing today add additional steps to implement multiple device VTH, TFT devices for loads in SRAMs, capacitors for DRAMs etc. • Process described here requires 16 masks (through metal 2) and > 100 process steps. • There are many possible variations on the process flow described here, some of which are described in Chapter 2 in the text. e.g. see the STI section in the text. Plummer et al.

  3. Modern CMOS Technology “0” ON PMOS in series “0” ON Vin=VL“0” Vout=VH“1” “1” Vout=VL“0” NMOS in parallel OFF OFF “0” “0” Vin=VH“1”

  4. CMOS with Two Level Metallization PMOS NMOS 16 photolithography steps and over 100 processing steps required in via plug Interlayer dielectric Oxide isolation Twin well technology

  5. Technology Overview Choose the substrate (type, orientation,resistivity, wafer size) 1 µm 80 nm • • Substrate selection: moderately • high resistivity, (100) orientation, • P type. • • Wafer cleaning, thermal oxidation • (≈ 40 nm), nitride (LPCVD) deposition ≈ 80 nm: • Photoresist • spinning and baking (≈ 0.5 - 1.0 µm). 40 nm Photolithography, UV • • Mask #1 patterns the active areas. • The nitride is dry etched in Fluorine plasma • Strip PR

  6. Isolation Si3N4 LOCOS= Local Oxidation of Silicon 1000 °C, 90 min H2O Xox= 0.5 µm Instead of Si3N4 use SiO2/PolySi/Si3N4= Poly Buffered LOCOS Results in less bird’s beak Shallow Trench Isolation STI 50-100 nm for less stress better packing density 10-20 nm Dry etch

  7. Si3N4 STI Isolation SiO2 lining for good interface Properties, corners rounding 10-20 nm thermally grown SiO2 (PE)CVD Oxide Oxide Filling Deposition by CVD, High Density Plasma

  8. Si3N4 Shallow Trench Isolation= STI SiO2 Planarization by CMP Chemical Medical Polishing High-ph slurry Flat holders Nitride used as a polishing stop Nitride removed before oxidation

  9. LOCOS • Field oxide is grown using a LOCOS process. Typically 90 min @ 1000 ˚C in H2O grows ≈ 0.5 µm. B Implant~150 keV, 1013cm-2 P-well fabrication PR Mask • Mask #2 blocks a B+ implant to form the wells for the NMOS devices. Typically 1013 cm-2 @ 150-200 KeV. Implantation Energy, Dose adjusted for depth (junction, masking) and concentration

  10. N-well fabrication Strip the PR (P-well), Deposit new PR and Pattern Implant P, 300-400 keV, ~1013cm-2 • Mask #3 blocks a P+ implant to form the wells for the PMOS devices. Annealing for N- and P-Wells Long time process High temperatures 2-3 µm deep • A high temperature drive-in produces the “final” well depths and repairs implant damage. Typically 4-6 hours @ 1000 ˚C - 1100 ˚C or equivalent Dt.

  11. Option 1 Process Options for Active Region and Well Formation PR Si3N4 Field Implant - increases dopant concentration under LOCOS oxide (the same mask) B at 50 keV and 1013cm-2 (Channel stop) SiO2 LOCOS oxide above highly doped Si Enhancement of diffusion by OXIDATION

  12. Formation of Wells Annealing after implantation Option 2 Buried and Epitaxial Layers p+ p Used in CMOS to prevent latchup Strip PR and Clean Wafers As (not P) buried layer 50 keV, 1015 cm-2 High dose

  13. Si3N4 Annealing in Oxygen(partly in H2O)= Selective (Si3N4) Oxidation And Diffusion of N+ Strip nitride Self-Aligned p+ Implantation B, 50-75 keV, ~1014cm-2

  14. Redistribution of implanted dopants Drive-in at 1000-1100 °C in N2 or Ar Strip oxide (HF, clean) No oxide needed now Epitaxy CVD 800-1000 °C Deposition of low (doped) concentration crystalline layers 1014-1020 cm-3, dxepi/dt~.5µm/min CVD using SiH4 or SiH2Cl2 with dopants B2H6, AsH3

  15. Formation of wells:LOCOS, N+ and P+ implantation, Drive-in Redistribution of diffusing dopants Gate Formation QI[cm-2]≈1-5x1012cm-2, E≈50-75 keV PR patterning Ion implantation for threshold voltage adjustment VTH=VFB+2ff+√2esNA(2ff)/COX PMOS NMOS VTH=VFB+2ff+√2esNA(2ff)/COX+qQI/ COX

  16. VT adjustment for PMOS PR patterning Ion implantation with low QI Strip PR • Mask #4 is used to mask the PMOS devices. A VTH adjust implant is done on the NMOS devices, typically a 1-5 x 1012 cm-2 B+ implant @ 50 - 75 KeV. • Mask #5 is used to mask the NMOS devices. A VTH adjust implant is done on the PMOS devices, typically 1-5 x 1012 cm-2 As+ implant @ 75 - 100 KeV.

  17. Gate Oxide • • The thin oxide over the • active regions is stripped • A new gate oxide • grown, typically 3 - 5 nm, • which could be grown in • 0.5 - 1 hrs @ 800 ˚C in O2 (adjust T, t) Deposition of Poly-Silicon= Gate Electrode Poly_Si • Polysilicon is deposited by LPCVD. LPCVD in silane at 600 °C, Thickness 0.3-0.5 µm • SiH4 Si +2H2 • An unmasked P+ or As+ (blank) implant dopes the poly (typically 5 x 1015 cm-2).

  18. Deposition of Poly-Silicon= Gate Electrode LPCVD in silane at 600 °C, Thickness 0.3-0.5 µm SiH4 Si +2H2 Ion implantation (blank) P or As High dose 5x1015cm-2 Gate Patterning PR lithography Mask #6 is used to protect the MOS gates. Dry etching in a chlorine- or bromine-based plasma = good selectivity to SiO2

  19. Gate Patterning Cut line PR lithography The poly is plasma etched using an anisotropic etch. Dry etching in a chlorine- or bromine-based plasma = good selectivity to SiO2 Along the cut line • Intel 90 nm technology transistor

  20. Extension (LDD) Formation LDD reduce short channel effects PR • • Mask #7 protects the PMOS • devices. A P+ (or As+) implant forms • the LDD regions in the NMOS • devices (typically 5 x 1013 cm-2 • @ 50 KeV). • LDD needs Low dose and low energy • Mask #8 protects the NMOS devices. A B+ implant forms the LDD regions in the PMOS devices (typically 5 x 1013 cm-2 @ 50 KeV). PR

  21. Conformal Deposition of SiO2 for spacers • Conformal layer of SiO2 is deposited by CVD or LPCVD (typically 0.5 µm). SiH4+O2 SiO2 +2H2 @400 °C SiH2Cl2 +N2O SiO2 +2N2 +2HCl @900 °C Anisotropic etch in fluorine plasma • Anisotropic etching leaves “sidewall spacers” along the edges of the poly gates.

  22. Source and Drain Formation High dose • • Mask #9 protects the PMOS • devices • An As+ implant forms • the NMOS source and drain • regions (typically 2-4 x 1015 cm-2 • @ 75 KeV). • High dose ensures low parasitic resistance • • Mask #10 protects the NMOS • devices, A B+ implant forms • the PMOS source and drain • regions (typically 1-3 x 1015 cm-2 • @ 50 KeV). • High dose not to exceed N+ in poly-Si

  23. Junction Formation and Defect Annealing • A final high temperature anneal drives-in the junctions and repairs implant damage (typically 30 min @ 900˚C or 1 min RTA @ 1000˚C. Oxide Removal Prior to Contact Formation • HF dip=oxide is selectively striped • An unmasked oxide etch allows contacts to Si and poly regions.

  24. Titanium Layer Deposition • Ti is deposited by sputtering (typically 100 nm). TiSi2 TiN Formation of TiSi2 Layer • The Ti is reacted in an N2 ambient, forming TiSi2 and TiN (typically 1 min @ 600 - 700 ˚C). • Reaction between Ti and Si @ 600 °C gives TiSi2 phase C45 = not conductive enough. At higher T C54 forms (more conductive)

  25. TiN PR Patterning of Tin Used As a Local Interconnect • Mask #11 is used to etch the TiN, forming local interconnects. TiN etched in NH4OH:H2O2:H2O PR strip (O2 ashing or wet) Anneal @≈800 °C for Rs reduction to 10 Ω/sq (TiN) and 1Ω/sq (TiSi2) • Intel 130 nm and 65 nm technology transistors.

  26. Multilevel Metal Formation BPSG Planarization necessary Deposit thick BSG or BPSG layer (B and P decrease reflow T) - not Adequate in small devices • A conformal layer of SiO2 is deposited by LPCVD (typically 1 µm). Planarization • Deposit PR layer and etch back - the same etch rates of SiO2 and PR ensure planarity • Better technique = CMP required for deep submicron devices. CMP is widely used to planarize the wafer surface.

  27. Patterning for Metallization • • Mask #12 is used to define the contact holes. • The SiO2 is etched. Anisotropy in etching important • Deposition (blanket) of • a thin (few tens of nm) TiN or Ti/TiN adhesion and diffusion barrier layer (CVD or sputtering) followed by • W as a conductive layer (CVD) WF6+3H2 W +6HF

  28. Planarization • CMP is used to planarize the wafer surface, completing the damascene process. • Metal Deposition • (sputtering forAl or electroplating for Cu) PR Sputtering of Al+Si+Cu against spiking and electromigration • Al is deposited on the wafer by sputtering. Mask #13 is used to pattern the Al and plasma etching is used to etch it.

  29. Planarization for Multilayer Metallization Protective layer: SiO2 or Si3N4 via • Intermetal dielectric and second level metal are deposited and defined in the same way as level #1. Mask #14 is used to define contact vias and Mask #15 is used to define metal 2. A final passivation layer of Si3N4 is deposited by PECVD and patterned with Mask #16. ILD • This completes the CMOS structure.

  30. • Cross section of chip structure from ITRS. Notice many of the features in the basic technology we just described. There are also additional features here that we will cover later in the quarter.

  31. Intel µprocessor chip 52MB SRAM chips on a 12” wafer • Photos of state-of-the-art CMOS chips (from Intel website). • 90 nm technology.

  32. Summary of Key ideas • This chapter serves as an introduction to CMOS technology. • It provides a perspective on how individual technologies like oxidation and ion implantation are actually used. • There are many variations on CMOS process flows used in industry. • The process described here is intended to be representative, although it is simplified compared to many current process flows. • Some process options are described in Chapter 2 in the text. • Perhaps the most important point is that while individual process steps like oxidation and ion implantation are usually studied as isolated technologies, their actual use is complicated by the fact that IC manufacturing consists of many sequential steps, each of which must integrate together to make the whole process flow work in manufacturing.

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