 Introduction with pictures  Prototype design and construction

CALICE - ECALsilicon-tungsten Introduction with pictures Prototype design and construction R&D on the design of the full scale calorimeter

e+e– W+W–at s = 800 GeV After reconstruction e+e– W+W–at s = 800 GeV Classified as charged pads Simulation,visualisation MOKKA, FANAL Classified as photon’s pads Just to recall the reason of the choice

Electron ID in jets ALL VALUES in % Photon ID in jets ZH at 500 GeV Z in  , H in jets Jets at 91 GeV Hadron MISID Electron ID Photon energy GeV Particle momentum GeV 250 GeV ± → • → and • →  ID Jet mass

Looking along the charged track in the first 4 X0 charged pion Photons from o Looking along the ch. track in 5-12 X0 Tau decays ID is essential for ID and polarisation measurement (250 GeV)→

Prototypes overview Global view of the test beam setup VME/PCI/… ECAL general view HCAL 2nd structure (2×1.4mm of W plates) 3rd structure (3×1.4mm of W plates) 180 mm BEAM ECAL Beam monitoring Movable table VFE 370 mm 1st structure (1.4mm of W plates) 370 mm Detector slab Silicon wafer

Mould for alveolus structure 1.4 Structure 5 alveolus :(10 layers) Detector slab (here it is just a type H structure) Alveolus structures Design and construction of a mould with all metallic pieces for the 3 different structures

Front End electronics Shielding Transverseview PCB Silicon wafer (0.525 mm) PCB (8-10 layers) ( 2 - 2.5 mm) Al. Shielding Silicon wafer (Cfi / W) structuretype H 7.3 mm Composite structure(0.15 mm / layer) Tungsten (1.4 mm, 2×1.4 or 3×1.4 mm) Detector slab

2 2 2 2 2 62mm 10mm 6 2 10mm Diode footprint 62mm 1 wafer Diode bias Sig. readout Diode pinout Detector schematic description Amorphous silicon deposition Protection Capacitance(AC coupling) Aluminium sheet PCB Wafers The aluminium sheet is the ground

4” high resistivity wafers • 525 microns thick – 5Kcm • tile side: 62.0 + 0.0 • - 0.1 mm • scribe line: 100 m • scribe safety zone: 200 m • guard ring width: cca 750 m • (cca 1.5 * wafer thickness) ECAL prototype silicon wafer description Dead zone width is only 1mm First test production with 25 wafers 24 good (<10nA leakage) Wafer book keeping information

CHIP FLC-PH1 developed at LAL Electronic readout Front End electronics • 18 charge inputs • 18 voltage outputs • 1 MUX voltage output low noise 1.6 nv/Hz good linearity non-linearity≲ 1% large dynamic 650 mip Custom-built VME readout board(UK) First prototype April 2003 Board based on PCI or even USB2.0 is also under study

Responsibilities ITEMS LABORATORIES - Tungsten production and testITEP, IHEP, LAL - Mechanics assembly (Cfi,…)LLR, LPC - Silicon wafers productionMSU (Moscow), IPASCR (Prague) - Amorphous silicon deposition,…PICM, LLR - VFE design and productionLAL, (LPC for large scale R&D) - ADC’s and DAQIC, UCL, Manchester, Cambridge , Birmingham - Detector slab assembly LLR - Cosmics test on assembled deviceLLR

Meetings and Agenda 21th January 2003 ,ORSAY(LAL) meeting on ECAL prototype - Technical meeting on construction , test, beam def., … End February 2003 ,PALAISEAU(LLR) meeting onDigital HCAL prototype - responsibilities - funding - repartition of works The goal is : ECAL ready for a first debugging test beam at theSummer-Fall 2004

Other R&D In progress at LLR Cooling of the readout Collaboration is welcome For the electronic readout inside the detector and if needed by the dissipation of the VFE - Study with SPICE and SAMCEF - Small prototype to validate the simulation - First response for Amsterdam 2003 Impact of e.m. shower on the VFE Collaboration is welcome - First study with GEANT4 - Possibility to use the beam H4 (CERN) with 200 GeV electron in 2003 - First response at the end of 2003 Under preparation By the LAL group

 Globalsimulation of the device withSPICE(static as well as dynamic simulation)  Localsimulation by finite elements usingSAMCEF(using the condition at the limit obtainsby SPICE)  Correlationandvalidationof the simulations by a small prototype  Simulation of a“large scale"detector slab and its environment. Cooling channel Heat points (VFE chip) Thermal sensors Externalconnections In progress at LLR Structure type H PCB 1mm thick(with wafers) Radiator aluminium plate

… T1 T2 T3 Degree K Point numbers R&D – 1st results SPICE/SAMCEF SPICE V = Temperature I =Calor flux SAMCEF T8 T7 T6 Temperature distribution : T5 T4 T1 T3 T2 T5 Results : T6 Conditions at the limits T4 T7 T8 T3 m m T2 0 8 1 8 0 m m T1

Conclusion The prototype design is almost fixed The prototype construction will begin soon Ready for a first test beam in 2004 The R&D on the large scale detector are in progress In both case, collaboration with US labs. is welcomed

 Introduction with pictures  Prototype design and construction