1 / 41

CMPE 3 2 5 Computer Architecture II

CMPE 3 2 5 Computer Architecture II. Cem Erg ün Eastern Med iterranean University. Using Assembly. Using Arrays for Counting. Consider the C code for counting an array where we have int target , int n , and int *list available in parameters $a0 - $a2 int count = 0; int i;

tamas
Download Presentation

CMPE 3 2 5 Computer Architecture II

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CMPE 325 Computer Architecture II Cem Ergün Eastern Mediterranean University Using Assembly

  2. Using Arrays for Counting • Consider the C code for counting an array where we have int target, int n, and int *list available in parameters $a0-$a2 int count = 0; int i; for (i = 0; i < n; i++) { if (list[i] == target) count++; } CMPE325 CH #3

  3. Using Arrays Solution • Writing the loop li $t0, 0 # count = 0 li $t1, 0 # i = 0 Loop: bge $t1, $a1, Exit # goto Exit if i >= n add $t2, $t1, $t1 # $t2 = 2 * i add $t2, $t2, $t2 # $t2 = 4 * i add $t3, $t2, $a2 # $t3 = list + 4 * i lw $t4, 0($t3) # $t4 = list[i] bne $t4, $a0, Next # goto Next if $t4!=target addi $t0, $t0, 1 # count++; Next: addi $t1, $t1, 1 # i++; j Loop # Loop again Exit: CMPE325 CH #3

  4. MIPS Assembler Directives • SPIM supports a subset of the MIPS assembler directives • Some of the directives include: • .asciiz – Store a null-terminated string in memory • .data – Start of data segment • .global – Identify an exported symbol • .text – Start of text segment • .word – Store words in memory • See Appendix A for details and examples CMPE325 CH #3

  5. Representing Instructions • High-level  Assembly  Machine .c C Program Compiler Assembly Program .s Assembler Module Object Machine Object .o Linker Executable Loader Memory CMPE325 CH #3

  6. Assembler • Expands macros and pseudoinstructions as well as converts values (ex. 0xFF for hex) • Primary purpose is to produce object file containing • Machine language instructions • Application data • Information for memory organization CMPE325 CH #3

  7. Object File • Includes • Object header – describes file organization • Text segment – machine code • Data segment – static and dynamic data • Relocation information – identifies instructions/data that depend on absolute addresses when program is loaded • Symbol table – list of labels that are not defined (ex. external references) • Debugging information – describes relationship between source code and machine instructions CMPE325 CH #3

  8. Linker • Linker combines multiple object modules • Identify where code/data will be placed in memory • Resolve code/data cross references • Produces executable if all references found • Steps • Place code and data modules in memory • Determine the address of data and instruction labels • Patch both the internal and external references • Separation between compiler and linker makes standard libraries an efficient solution to maintaining modular code CMPE325 CH #3

  9. Loader • Loader used at run-time • Reads executable file header for size of text/data segments • Create address space sufficiently large • Copy instructions and data from executable into memory • Copy parameters to main program’s stack • Initialize machine registers and set SP • Jump to start-up routine • Makes exit system call when program is done CMPE325 CH #3

  10. Instruction Encoding • As we have seen, there are several different ways that instructions are written, depending upon what types of information they need • MIPS architecture has three instruction formats, all 32 bits in length • Regularity is simpler and improves performance • A 6 bit opcode appears at the beginning of each instruction • Needed by control logic to be able to decode instruction type • See Appendix A.10 and Page 153 for a list CMPE325 CH #3

  11. Machine Language • All instructions have the same length (32 bits) • DP3: Good design demands good compromises • Same length or same format • Three different formats • R: arithmetic instruction format • I: transfer, branch, immediate format • J: jump instruction format • add $t0, $s1, $s2 • 32 bits in machine language • Fields for: • Operation (add) • Operands ($s1, $s2, $t0) 10101101001010000000010010110000 00000010010010000100000000100000 10001101001010000000010010110000 lw $t0, 1200($t1) add $t0, $s2, $t0 sw $t0, 1200($t1) A[300] = h + A[300]; CMPE325 CH #3

  12. Instruction Formats 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits R: op rs rt rd shamt funct I: op rs rt address / immediate J: op target address op: basic operation of the instruction (opcode) rs: first source operand register rt: second source operand register rd: destination operand register shamt: shift amount funct: selects the specific variant of the opcode (function code) address: offset for load/store instructions (+/-215) immediate: constants for immediate instructions CMPE325 CH #3

  13. Example A[300] = h + A[300]; /* $t1 <= base of array A; $s2 <= h */ Compiler lw $t0, 1200($t1) # temporary register $t0 gets A[300] add $t0, $s2, $t0 # temporary register $t0 gets h +A[300] sw $t0, 1200($t1) # stores h + A[300] back into A[300] Assembler 35 9 8 1200 0 18 8 8 0 32 43 9 8 1200 100011 01001 01000 0000 0100 1011 0000 000000 10010 01000 01000 00000 100000 101011 01001 01000 0000 0100 1011 0000 CMPE325 CH #3

  14. R-Format • Used by ALU instructions • Uses three registers: one for destination and two for source • Function code specifies which operation Bits 6 5 5 5 5 6 OP=0 rs rd sa funct rt Function Code Second SourceRegister First SourceRegister ResultRegister Shift Amount (Chap 4) CMPE325 CH #3

  15. Bits 6 5 5 5 5 6 OP=0 17 8 0 32 18 Function Code Second SourceRegister First SourceRegister ResultRegister Shift Amount (Chap 4) R-Format Example • Consider the add instruction add $8, $17, $18 • We can fill in each of the fields 000000 10001 01000 00000 100000 10010 CMPE325 CH #3

  16. R-Format Limitations • The R-Format works well for ALU-type operations, but does not work well for some of the other instructions we have seen • Consider for example the lw instruction which takes an offset • If placed in an R-format, would only have 5 bits of space for the offset • Offsets of only 32 are not all that useful!  A good design requires good compromises, so a single instruction format is not possible CMPE325 CH #3

  17. Immediates (Numerical Constants) • Small constants are used frequently (50% of operands) • A = A + 5; • C = C – 1; • Solutions • Put typical constants in memory and load them • Create hardwired registers (e.g. $0 or $zero) • Rule4: make the common case fast • MIPS instructions for constants (I format) • addi $t0, $s7, 4 # $t0 = $s7 + 4 4 8 23 8 4 001000 10111 01000 0000 0000 0000 0100 CMPE325 CH #3

  18. I-Format • The immediate instruction format • Uses different opcodes for each instruction • Immediate field is signed (positive/negative) • Used for loads and stores as well as immediate instructions (addi, lui, etc.) • Also used for branches since branch destination is PC relative Bits 6 5 5 16 OP rs imm rt Immediate Second SourceRegister First SourceRegister CMPE325 CH #3

  19. I-Format Example • Consider the addi instruction addi $8, $9, 1 # $t0 = $t1 + 1 • Fill in each of the fields Bits 6 5 5 16 8 9 1 8 Immediate Second SourceRegister First SourceRegister 001000 01001 0000000000000001 01000 CMPE325 CH #3

  20. Another I-Format Example • Consider the while loop from before Loop: add $t0, $s0, $s0 # $t0 = 2 * i add $t0, $t0, $t0 # $t0 = 4 * i add $t1, $t0, $s3 # $t1 = &(A[i]) lw $t2, 0($t1) # $t2 = A[i] bne $t2, $s2, Exit # goto Exit if != add $s0, $s0, $s1 # i = i + j j Loop # goto Loop Exit: • Pretend the first instruction is located at address 80000 CMPE325 CH #3

  21. I-Format Example (Incorrect) • Consider the bne instruction bne $t2, $s2, Exit # goto Exit if $t0 != $S5 • Fill in each of the fields • This is not the optimum encoding Bits 6 5 5 16 5 10 8 18 Immediate Second SourceRegister First SourceRegister 000101 01010 0000000000001000 10010 CMPE325 CH #3

  22. PC Relative Addressing • What can we improve about our use of immediate addresses when branching? • Since instructions are always 32 bits long, and since addressing is word aligned, we know that every address must be a multiple of 4 • Therefore, we actually branch to the address that is PC + 4 + 4  immediate CMPE325 CH #3

  23. PC Relative Addressing Memory byte addr. PC relative word addr. Branch instructions use PC-relative Addressing. Target is the label of address (B) in instruction memory. 0000 Farthest backward branch address A−217: 215 lw $t3,8($s4) negative imm16 = −k and $s0,$s1,$t0 −k ref. point is next instruction A−4: beq $s0,$s1,B −1 PC-relative byte address = B – A A: addi $s3,$s3,5 0 positive imm16 =k =(B−A)/4 Target-Address = B= PC + 4×Imm16 B: k sub $t0,$s1,$t1 PC contains address of the next instruction = A A+217-1: 215-1 slti $at,$s1,$t0 Farthest forward branch address 16-bit signed Immediate word address relative to next instruction = k = (B–A)/4 FFFF CMPE325 CH #3

  24. I-Format Example (Corrected) • Re-consider the bne instruction bne $t2, $s2, Exit # goto Exit if $t0 != $S5 • Use PC-Relative addressing for the immediate Bits 6 5 5 16 5 10 2 18 Immediate Second SourceRegister First SourceRegister 000101 01010 0000000000000010 10010 CMPE325 CH #3

  25. Branching Far Away • If the target is > 216 away, then the compiler inverts the condition and inserts an unconditional jump • Consider the example where L1 is far away beq $s0, $s1, L1 # goto L1 if S$0=$s1 • Can be rewritten as bne $s0, $s1, L2 # Inverted j L1 # Unconditional jump L2: CMPE325 CH #3

  26. Far Target Address Text Segment (252MB) 0x00400000 (0x07fe0000) -217 PC (0x08000000) beq $s0, $s1, L1 +217 (0x08020000) bne $s0, $s1, L2 j L1 L2: (0x08200000) L1: 0x10000000 CMPE325 CH #3

  27. I-Format Example: Load/Store • Consider the lw instruction lw $t2, 0($t1) # $t2 = Mem[$t1] • Fill in each of the fields Bits 6 5 5 16 35 9 0 10 Immediate Second SourceRegister First SourceRegister 001000 01001 0000000000000000 01010 CMPE325 CH #3

  28. Direct Memory Addressing • When loading/storing, sometimes it is necessary to address a full 32 bits • Many options, including: • Use a 32 bit constant already stored in a register lw $t1, 0($t0) # Load using register $t0 • Load an address constant from a table in memory lw $t0, 40($s0) # Load the 32 bit address lw $t1, 0($t0) # Load contents at address CMPE325 CH #3

  29. J-Format • The jump instruction format • Uses different opcodes for each instruction • Used by j and jal instructions • Uses absolute addressing since long jumps are common • Uses word addressing as well (target  4) • Pseudodirect addressing where 228 bits from target, and remaining 4 bits come from upper bits of PC Bits 6 26 OP target Jump Target Address CMPE325 CH #3

  30. J-Format • Address-to-Jump = Page-Address+4×imm26 = (PC31, PC30, PC29, PC28, I25, I24,....., I1, I0, 0 , 0)two shift-left 2-bit to convert the word-address to the byte-address. Memory Page Address. Leftmost-4-bits of the Program Counter. 26-bit Immediate word- address. CMPE325 CH #3

  31. Complete Example • Now we can write the complete example for our while loop 80000 0 16 8 0 32 16 80004 0 8 8 0 32 8 80008 0 8 9 0 32 19 80012 35 9 0 10 80016 5 10 2 18 80020 0 16 16 0 32 17 80024 2 20000 80028 … CMPE325 CH #3

  32. SPIM Code PC MIPS Pseudo MIPS add $9, $10, $11 main: add $t1, $t2, $t3 j 0x00400048 / 4 [exit] j exit addi $9, $10, -50 addi $t1, $t2, -50 lw $8, 5($9) lw $t0, 5($t1) lw $8, -5($9) lw $t0, -5($t1) bne $8, $9, 4 [exit-PC]#(48-38)=10H=16/4 bne $t0, $t1, exit addi $9, $10, 50 addi $t1, $t2, 50 bne $8, $9, -8 [main-PC]#(20-40)=-20H=-32/4 bne $t0, $t1, main lb $8, -5($9) lb $t0, -5($t1) j 0x00400020 / 4[main-PC] j main add $9, $10, $11 exit: add $t1, $t2, $t3 main [0x00400020] [0x00400024] [0x00400028] [0x0040002c] [0x00400030] [0x00400034] [0x00400038] [0x0040003c] [0x00400040] [0x00400044] [0x00400048] exit CMPE325 CH #3

  33. Addressing Modes 1 . I m m e d i a t e a d d r e s s i n g o p r s r t I m m e d i a t e 2 . R e g i s t e r a d d r e s s i n g o p r s r t r d . . . f u n c t R e g i s t e r s R e g i s t e r 3 . B a s e a d d r e s s i n g M e m o r y o p r s r t A d d r e s s + B y t e H a l f w o r d W o r d R e g i s t e r 4 . P C - r e l a t i v e a d d r e s s i n g o p r s r t A d d r e s s * 4 M e m o r y + W o r d P C 5 . P s e u d o d i r e c t a d d r e s s i n g o p A d d r e s s * 4 M e m o r y W o r d P C CMPE325 CH #3

  34. Addressing Modes 1- Register Addressing • A register address field is always 5-bit • jr $31 • add $3, $8,$9 CMPE325 CH #3

  35. Addressing Modes 2- Base&Displacement Addressing • sw $5, 300 ($7) 16-bit imm CMPE325 CH #3

  36. Addressing Modes 3- Immediate addressing • immediate arithmetic-logic instructions (addi, andi, ori, slti, lui) addi and slti use sign-extend All logical instructions use zero-extend 16-bit imm CMPE325 CH #3

  37. Addressing Modes 4- PC-relative addressing • beq and bne use PC-relative addressing CMPE325 CH #3

  38. Addressing Modes 5- Pseudo-Direct addressing • An operand may contain large part of the address directly. • J and JAL has 26-bit immJ field as direct address. • This field is left shifted-2-bit, and then PC-extended. 28-bit byte address is PC-extended to 32-bit. CMPE325 CH #3

  39. Addressing Modes Summary • Register addressing – operand is a register(ex. ALU) • Base/displacement addressing – operand is at the memory location that is the sum of a base register and a constant (ex. load/store) • Immediate addressing – operand is a constant within the instruction itself (ex. constants) • PC-relative addressing – address is the sum of PC and constant in instruction (ex. branch) • Pseudodirect addressing – target address is concatenation of field in instruction and the PC (ex. jump) CMPE325 CH #3

  40. Four Design Principles • Simplicity favors regularity • Smaller is faster • Good design demands good compromises • Make the common case fast CMPE325 CH #3

  41. CMPE325 CH #3

More Related