ECE 331 – Digital System Design

1. Electrical characteristics of logic gates, Timing characteristics of logic gates, and Electrical and timing constraints in logic circuits (Lecture #13) ECE 331 – Digital System Design The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney, and were used with permission from Cengage Learning.

2. ECE 331 - Digital System Design Representing Logic Values • In a real circuit, logic values must be represented by an electrical characteristic. • In TTL and CMOS circuits, voltage levels, or more accurately, voltage ranges are used to represent each of the logic values. • These voltage ranges are specified in the data sheet for each of the standard components. • They must be considered when designing (and building) combinational logic circuits.

3. Voltage VDD supply voltage Logic 1 V1,min Undefined V0,max Logic 0 VSS ground Representing Logic Values

4. ECE 331 - Digital System Design Representing Logic Values • There are 4 voltages defined for each standard logic gate. • VOH Output-High Voltage • VOL Output-Low Voltage • VIH Input-High Voltage • VIL Input-Low Voltage • The logic values, logic 0 and logic 1, are defined by these voltages.

5. ECE 331 - Digital System Design VIH VOH VIL VOL Representing Logic Values • VIL and VIH specify the voltages that define the voltage range for logic 0 and logic 1, respectively, at the input of the logic gate. • VOL and VOH specify the voltages that define the voltage range for logic 0 and logic 1, respectively, at the output of the logic gate.

6. Voltage VDD supply voltage Logic 1 (output) VOH Logic 1 (input) VIH Undefined VIL Logic 0 (input) VOL Logic 0 (output) VSS ground Representing Logic Values

7. ECE 331 - Digital System Design Current Limits • Standard logic devices are limited by how much current they can source and how much current they can sink. • There are 4 currents defined for each standard logic gate. • IOH Output-High Current (source) • IOL Output-Low Current (sink) • IIH Input-High Current (source) • IIL Input-Low Current (sink) • These currents determine how many logic gates can be interconnected.

8. ECE 331 - Digital System Design Logic Gate Delay • A standard logic gate does not respond to a change in its input(s) instantaneously. • There is, instead, a finite delay between a change in the input and a change in the output. • The propagation delay of a standard logic gate is defined for two cases: • tPLH = delay for output to change from low to high • tPHL = delay for output to change from high to low

9. ECE 331 - Digital System Design Logic Gate Delay

10. ECE 331 - Digital System Design Logic Gate Delay • The gate delay (or propagation delay) is used to determine • When outputs are valid • The maximum speed of a combinational logic circuit • The maximum frequency of a sequential logic circuit

11. ECE 331 - Digital System Design 74LS04 (NOT Gate) Standard Logic Device

12. ECE 331 - Digital System Design 74LS04 (NOT Gate) Standard Logic Device

13. ECE 331 - Digital System Design 74LS08 (AND Gate) Standard Logic Device

14. ECE 331 - Digital System Design 74LS08 (AND Gate) Standard Logic Device

15. ECE 331 - Digital System Design 74LS32 (OR Gate) Standard Logic Device

16. ECE 331 - Digital System Design 74LS32 (OR Gate) Standard Logic Device

17. ECE 331 - Digital System Design Noise Margin • Noise margin is a measure of the noise immunity provided by a digital logic circuit. • Noise margin is dependent upon the characteristic voltages specified for the standard logic devices. • Noise margin is specified for both the logic 0 value and the logic 1 value: • NMH = VOH – VIH Noise Margin High • NML = VIL – VOL Noise Margin Low

18. Voltage VDD supply voltage VOH NMH VIH Undefined VIL NML VOL VSS ground Noise Margin

19. ECE 331 - Digital System Design Fan-out • Fan-out is the number of gate inputs that can be properly driven by a single gate output • Current must flow between logic gates • Current requirements are dictated by logic gate technology (i.e. the logic family). • Current limits fan-out • DC Fan-out is the fan-out when the output is at steady-state. • Both high (1) and low (0) output states must be considered when implementing logic circuit design • Select worst-case as limit

20. ECE 331 - Digital System Design N 1 f To inputs of x n other inverters Fan-out Fan-out is determined by taking the ratio of the output current (IOH, IOL) of the driving device to the input current (IIH, IIL) of the load device(s).

21. ECE 331 - Digital System Design Fan-out • Low-state Fan-out = Floor[ IOL_max (driver) / IIL_max (load) ] • High-state Fan-out = Floor[ IOH_max (driver) / IIH_max (load) ] • Design the logic circuit based on the minimum of the two fan-out limits.

22. ECE 331 - Digital System Design Fan-out • Exceeding fan-out limits leads to • Increase in output-low voltage (VOL) • And possibly the wrong logic state • Decrease in output-high voltage (VOH) • And possibly the wrong logic state • Increase in temperature • And possible destruction of the circuit / device • Increase in propagation delay

23. ECE 331 - Digital System Design V for n = 1 f V DD V for n = 4 f Gnd 0 Time (c) Propagation times for different values of n Effect of Fan-out on Gate Delay

24. ECE 331 - Digital System Design Electrical Constraints in Circuit Design • Devices in the same logic family have the same electrical characteristics. • Devices in different logic families often have different electrical characteristics. • In order to interconnect devices of different logic families: • Must consider the voltage levels of the driving and load devices. • Must consider the current sourced and sunk by the driving and load devices, respectively.

25. ECE 331 - Digital System Design Electrical Constraints in Circuit Design • Voltage • The VOH of the driving device must be greater than the VIH of the load device. • The VOL of the driving device must be less than the VIL of the load device. • Must consider the noise margin • Current • The driving device sources current for one or more load devices. • Must consider the fan-out limit for the driving device.

26. ECE 331 - Digital System Design Example: Determine the following constraints when designing a circuit using NAND (74xx00) gates only: 1. What is the noise margin when one 74LS00 drives another 74LS00? 2. What is the fan-out limit for the 74LS00 when driving one or more 74LS00 gates? Electrical Constraints in Circuit Design

27. ECE 331 - Digital System Design

28. ECE 331 - Digital System Design Electrical Constraints in Circuit Design • From the 74LS00 data sheet: • VOH_min = 2.7 V VOL_max = 0.4 V • VIH_min = 2.0 V VIL_max = 0.8 V • High Noise Margin • NMH = 2.7 V – 2.0 V = 0.7 V • Low Noise Margin • NML = 0.8 V – 0.4 V = 0.4 V

29. ECE 331 - Digital System Design

30. ECE 331 - Digital System Design Electrical Constraints in Circuit Design • From the 74LS00 data sheet: • IOH_max = - 0.4 mAIOL_max = 8.0 mA • IIH_max = 20 mAIIL_max = - 0.4 mA • Low-state fanout = • Floor[ 8.0 mA / 0.4 mA ] = 20 • High-state fanout = • Floor[ 0.4 mA / 20 mA ] = 20

31. ECE 331 - Digital System Design Example: Determine the following constraints when designing a circuit using NAND (74xx00) gates only: 1. What is the noise margin when a 74LS00 drives a 74HC00? 2. What is the fan-out limit for the 74LS00 when driving one or more 74HC00 gates? Electrical Constraints in Circuit Design

32. ECE 331 - Digital System Design

33. ECE 331 - Digital System Design Electrical Constraints in Circuit Design • From the 74LS00 data sheet: • VOH_min = 2.7 V VOL_max = 0.4 V • From the 74HC00 data sheet: • VIH_min = 3.15 V VIL_max = 1.35 V • High Noise Margin • NMH = 2.7 V – 3.15 V = - 0.45 V • Low Noise Margin • NML = 1.35 V – 0.4 V = 0.95 V

34. ECE 331 - Digital System Design Electrical Constraints in Circuit Design • From the 74LS00 data sheet: • IOH_max = - 0.4 mA IOL_max = 8.0 mA • From the 74HC00 data sheet: • IIH_max = IIL_max = +/- 1 mA • Low-state fanout = • Floor[ 8.0 mA / 1 mA ] = 8000 • High-state fanout = • Floor[ 0.4 mA / 1 mA ] = 400

35. ECE 331 - Digital System Design Timing Constraints in Circuit Design Simple Analysis • Given: A logic circuit with multiple inputs and a single output. • Given: A single transition on one of the inputs. • Determine: The propagation delay between the input transition and the output transition. • Identify the path between the input on which the transition occurred and the output. • Calculate the propagation delay (for the circuit) using the gate delay for each gate in the path. • Gate delay is specified in the datasheet.

36. ECE 331 - Digital System Design Timing Constraints in Circuit Design More Complex Analysis • Problem: Some circuits have more than one path from an input to an output. • Solution: • Analyze every possible delay path or • Use the Worst Case Analysis • Provides a conservative specification • Often sufficient

37. ECE 331 - Digital System Design Timing Constraints in Circuit Design More Complex Analysis • Problem: What if multiple inputs change at the same time? • Solution: • Analyze all combinations of input changes for all delay paths (to the output). or • Use the Worst Case Analysis

38. ECE 331 - Digital System Design Timing Constraints in Circuit Design Sum of Worst Cases (SWC) Analysis • Write worst case delay next to each logic gate • Select maximum of tPLH and tPHL • Identify all input-output paths (i.e. all delay paths) • Calculate worst case delay for each path • Summarize in table • Select worst case (i.e. maximum propagation delay)

39. ECE 331 - Digital System Design Example: Using the Sum of Worst Cases (SWC) Analysis, determine the maximum propagation delay for the Exclusive-OR (XOR) Logic Circuit. Timing Constraints in Circuit Design

40. ECE 331 - Digital System Design A 74LS08 B 74F04 F 74F32 74LS04 74F08 Example:

41. ECE 331 - Digital System Design A 74LS08 B 74F04 F 74F32 74LS04 74F08 Example: tPD = 26.1 ns

42. ECE 331 - Digital System Design A 74LS08 B 74F04 F 74F32 74LS04 74F08 Example: tPD = 27.3 ns

43. ECE 331 - Digital System Design A 74LS08 B 74F04 F 74F32 74LS04 74F08 Example: tPD = 32.1 ns

44. ECE 331 - Digital System Design Example: A 74LS08 B 74F04 F 74F32 74LS04 74F08 tPD = 12.3 ns

45. ECE 331 - Digital System Design Example: Worst Case Propagation Delay = 32.1 ns

46. ECE 331 - Digital System Design Questions?