DLL ck

1. DLL latches Encoder latches 50 states DLL ck DLL to TDC encoder QIE ck delay D Q D Q Ck Ck Heart of the TDC Discrim logic Single pulse operation: Latch the DLL state If the Discrim fired in Bucket 1, then clock the DLL latch contents into the Encoder latches here DLL ck Discrim 500 ps SINGLE PULSE WORKS FINE! 44 45 46 47 48 49 0 1 2 3 Bucket 2 Bucket 1 (Code 62 = starts high) (Code 63 = nothing happened) TDC results for Bucket 1, Bucket 2: 48,62 49,62 49,0 63,0 63,1

2. Double pulse operation: TDC reads out “last” pulse in the bucket, with some problems Latch DLL Latch DLL again 2nd pulse overwrites the 1st pulse DLL ck Clock the DLL latch contents into the Encoder latches here Discrim Works OK like this 44 45 46 47 48 49 0 1 2 3 PROBLEM AREAS If Hit 1 occurs in the first half of the bucket, then a Hit 2 in bin 49 reads out as a 0, not 49 as it should. Hit 2 in next bucket still overwrites Hit 1 Possible garbage (this zone is ~100 ps wide) Both hits get recorded properly in different buckets Discrim Hit 1 Hit 2 44 45 46 47 48 49 0 1 2 3 If the Discrim fires here, the DLL latch output is changing to a new value while being clocked into the Encoder latch: possible garbage! In this case, the TDC just reports the most recent valid code, whatever it was.

3. Modification to accept first hit only Inhibit until after garbage zone Discrim ignored Hit 1 Hit 2 Discrim inhibit Add a discriminator inhibit signal (A Hit 2 in bin 0 will now be recorded in bin 1) garbage zone new DLL latch ck 44 45 46 47 48 49 0 1 2 3 Minimum discrim pulse width = 1 ns One possible situation: Hit 2 drops right after the inhibit goes away Discrim Hit 1 Hit 2 Discrim inhibit Therefore, a too-narrow DLL latch ck pulse may result. However, we don’t care, since this bucket will put out a 62 (starts high). new DLL latch ck

4. Discriminator Hysteresis: is it sufficient? Transresistance of timing amplifier: 1.8 mV/uA [(discriminator input voltage)/(QIE input current)] Discriminator threshold bin size = 3.7 uA (~ 7 mV at discriminator input) Pk-pk noise of timing circuit, seen at discriminator input: ~ 6 mV (3.4 uA at QIE input) Hysteresis of the discriminator: ~ 2 mV

5. Discriminator threshold set to ~ 10 uA QIE input pulse 10 uA input Discriminator output 12 uA input 100 ns/div 50 ns/div

6. Proposed changes to QIE10_P6 • Redesign the TDC for first pulse instead of last pulse: add a discriminator inhibit so that after the first pulse in a bucket latches the DLL data, further discriminator pulses are not allowed until bin 1 of the next bucket. • Add a new “Invalid” code to the TDC. If for any reason the Encoder latches garbage (like a SEU), the new Invalid code is output instead of a code that looks legitimate. • Consider adding a program bit to disable the reporting of NoLockwith dedicated TDC code 61. This information is also available on the CMOS NoLock output pin. It is possible for a fake NoLock signal (lasting just one or very few clock periods) to be generated by a SEU (as opposed to actual loss of DLL lock). This would cause loss of legitimate TDC data due to the reporting of a fake NoLock through the TDC. • Any modifications to the discriminator hysteresis??