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Chapter 8. Introduction to Sequential Logic. Sequential Circuit. A digital circuit whose output depends not only on the present combination of input, but also on the history of the circuit. Sequential Circuit Elements. Two basic types: Latch Flip-flop
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Chapter 8 Introduction to Sequential Logic
Sequential Circuit • A digital circuit whose output depends not only on the present combination of input, but also on the history of the circuit.
Sequential Circuit Elements • Two basic types: • Latch • Flip-flop • The difference is the condition under which the stored bit changes.
Sequential Circuit Inputs • The LATCH is a sequential circuit with two inputs (SET and RESET). • SET – an input that makes the device store a logic 1. • RESET – an input that makes the device store a logic 0.
Sequential Circuit Outputs • Two complementary outputs • Outputs are always in opposite logic states.
Active HIGH or LOW Inputs • Latches can have either active HIGH or active LOW inputs. • The output of the LATCH, regardless of the input active level, is still defined as:
Function 0 0 1 1 Forbidden 0 1 1 0 SET 1 0 0 1 RESET 1 1 No Change NAND Latch Function Table
Function Table Notation • Qt indicates the present state of the Q input. • Qt +1 indicates the value of Q after the specified input is applied.
NAND Latch Operation • Two possible stable states: • SET • RESET • Feedback keeps the latch in a stable condition.
Block Diagram File NAND Latch • Gate components are called BOR2: • Bubbled-OR, 2-inputs • Inputs are labeled nS and nR. • Outputs are labeled Q and nQ. • In Quartus, the n prefix takes the place of the logic inversion bar.
Practical Synthesis of theNAND Latch • Quartus II does not synthesize the LATCH exactly as shown in Figure 8.15 on the previous slide. • Quartus II analyzes the Boolean equation of the original LATCH and reformats the circuit to fit the target device.
Switch Bounce • The condition where the closure of a switch contact results in a mechanical bounce before the final contact is made. • In logic circuits, switch bounce causes several pulses when a switch is closed. • Can cause circuit to behave unpredictably.
Switch Debounce Circuit • Uses a NAND latch with switch contacts connected to +5 volts. • Bounce is ignored since that condition results in inputs of: • A no-change condition
Gated SR Latch • The time when a latch is allowed to change state is regulated. • Change of state is regulated by a control signal called ENABLE. • Circuit is a NAND latch controlled by steering gates.
Latch ENABLE Input • Used in two principal ways: • As an ON/OFF signal • As a synchronizing signal
Gated D or Transparent Latch • A latch whose output follows its data input when its ENABLE input is active. • When ENABLE is inactive, the latch stores the data that was present when ENABLE was last active.
D Latches in Quartus II • Can be implemented as a primitive in a Block Diagram file (.bdf). • Can be implemented with a behavioral or structural description in a VHDL file.
VHDL Process Statement • PROCESS statement is concurrent. • Statements inside the PROCESS are sequential.
-- d_latch_vhdl.vhd -- D latch with active-HIGH level-sensitive enable ENTITY d_latch_vhdl IS PORT( d, ena : IN BIT; q : OUT BIT); END d_latch_vhdl; VHDL – D Latch – 1
ARCHITECTURE a OF d_latch_vhdl IS BEGIN PROCESS ( d, ena) BEGIN IF ( ena = ‘1’) THEN q <= d; END IF; END PROCESS; END a; VHDL – D Latch – 2
Instantiating a Latch Primitive • Primitive is contained in the Altera library, in a package called maxplus2. • Component declaration in maxplus2 package. • Unnecessary to declare it in the file used.
-- latch_primitive.vhd -- D latch with active-HIGH level-sensitive enable LIBRARY ieee; USE ieee.std_logic_1164.ALL; LIBRARY altera; USE altera.maxplus2.ALL; VHDL – Latch Primitive – 1
ENTITY latch_primitive IS PORT( d_in, enable : IN STD_LOGIC; q_out : OUT STD_LOGIC); END latch_primitive; VHDL – Latch Primitive – 2
ARCHITECTURE a OF latch_primitive IS BEGIN -- Instantiate a latch from a QUARTUS II primitive latch_primitive: latch PORT MAP (d => d_in, ena => enable, q => q_out); END a; VHDL – Latch Primitive – 3
Multibit Latches in VHDL • VHDL can be used to implement latches with multiple D inputs and Q outputs and a common ENABLE line. • Use behavioral description with STD_LOGIC_VECTOR types. • Use primitives – predefined components. • Use component from Library of Parameterized Modules (LPM).
-- latch4_behavioral.vhd -- D latch with active-HIGH level-sensitive enable -- uses a latch component from the -- Library of Parameterized Modules (LPM) LIBRARY ieee; USE ieee.std_logic_1164.ALL; --required for STD_LOGIC types LIBRARY lpm; USE lpm.lpm_components.ALL; -- Required for LPM components VHDL – Latch LPM Component – 1
ENTITY latch4_lpm IS PORT(d_in : IN STD_LOGIC_VECTOR(3 downto 0); enable : IN STD_LOGIC; q_out : OUT STD_LOGIC_VECTOR(3 downto 0)); END latch4_lpm; VHDL – Latch LPM Component – 2
ARCHITECTURE a OF latch4_lpm IS BEGIN -- instantiate latch from an LPM component latch4 : lpm_latch GENERIC MAP (LPM_WIDTH => 4) PORT MAP ( data => d_in, gate => enable, q => q_out); END a; VHDL – Latch LPM Component – 3
Flip-Flop Definition • A gated latch with a clock input. • The sequential circuit output changes when its CLOCK input detects an edge. • Edge-sensitive instead of level-sensitive.
CLOCK Definitions • Positive edge: • The transition from logic ‘0’ to logic ‘1’ • Negative edge: • The transition from logic ‘1’ to logic ‘0’ • Symbol is a triangle on the CLK (clock) input of a flip-flop.