CEBE Seminar Digitaalsüsteemide diagnostika Jäneda mõis, Juuni 17, 2013

CEBE SeminarDigitaalsüsteemide diagnostikaJäneda mõis, Juuni 17, 2013 Raimund Ubar

CEBE koostööruumi dimensioonid Koostöö otsingud CEBE koostöö P1 P2 P5 P7

Valitud tulemusi diagnostika valdkonnas • 1. Kõrgtaseme otsustusdiagrammid (KTOD - HLDD) • 2. Digitaalsüsteemide formaalne verifitseerimine ja disainivigade automaatne parandamine • digitaalsüsteemide kanooniline mudel – HLDD esitus karakteristlike polünoomidena • mudeli ja meetodite eelisteks on parem skaleeruvus tänu ülesande originaalsele tükeldamisviisile • 3. Digitaalsüsteemide diagnostika • rikete simulaator (kiirem kommertssimulaatoritest) • testide generaatorid • rikete diagnostika uudne kontseptsioon: • rikete testimise taandamine skeemi korrasoleku tõestamisele • vabanemine rikete mudelitest ja vastastikkusest maskeerimisest

1. Kõrgtaseme otsustusdiagrammid VHDL description of 4 processes for a simple Control Unit

1. Kõrgtaseme otsustusdiagrammid - süntees DDs forstate, enable_inand nstate 1 state rst #1 0 1 nstate clk 0 state’ nstate 1 0 state’ #1 enable_in 1 2 0 rb0 #2 1 1 enable_in clk enable 0 enable’ Superposition of DDs

state 1 rst #1 0 0 1 state’ #1 enable' 2 1 0 rb0 #2 1 0 1 outreg fin reg_cp reg enable state #0001 1 2 #0011 0 0 #1100 enable rb0 1 1 #0100 #0010 1. Kõrgtaseme otsustusdiagrammid - süntees HLDD model for the Control Unit

1. Kõrgtaseme otsustusdiagrammid - näide Each node in SSBDD represents a signal path: Control path The faults at y3 in HLDD represent the faults in the control circuitry and in the multiplexer M3 in the RTL circuit The faults at R1*R2 in HLDD represent the faults in multiplier, input and output buses, and in the registers Data path

2. Digitaalsüsteemide verifitseerimine System specification System buggy RTL implementation New variables appeared: reg t and state The order of checking predicate values is also changed A copy-paste error: condition c_c should hold when we are adding in c, not the negation of c_c Bug

2. Digitaalsüsteemide verifitseerimine Implementation Specification Each graph has a unique polynomial Canonical Form of HLDDs Novelty: Boolean methods can be generalized in a straightforward way to higher functional levels

2. Disainivigade parandamine P(w,vT) p(v,w) v0 P(v0,v) v w vT For every node w in HLDD define a subgraph Gw of G with root node w and all descendant nodes (with polynomial P(w,vT)) For every pair of nodes v, w we define a subgraph Gv,wwith root node vand a single terminal node w (with polynomial p(v,w)) Correction procedure: P(w’,vT) w' Terminal node with faulty P(v0,vT) Root node Modification of the HLDD P(v0, vT) = P(v0,v) p(v,w)  [ P(w’,vT)- P(w,vT) ]

2. Keerukusega võitlemisest - skaleeruvus High-Level Decision Diagrams Program data flow D E Behavior of A State space C A=FA1 (...) B B=FB1 (...) C=FC1 (...) A=FA2 (B,C,...) Novelty: Instead of reasoning the design as a whole, it will be partitioned into the behavioral sub-models of functional variables (HLDDs) A=FAn (D,E,...)

y y y y 1 2 3 4 a R · c 1 M + 1 e · M R 3 2 b · * M · 2 IN · d 3. Testide genereerimine registertasandil High-level test generation with DDs: Scanning test Decision Diagram Single path activation in a single DD Data function R1* R2is tested R 2 0 y # 0 4 Control path 1 R 2 Data path 0 0 2 y y R + R 3 1 1 2 1 IN + R 2 1 IN 2 R 1 3 0 y R * R 2 1 2 1 IN* R 2 Test program: Control: y1 y2 y3 y4 = 0032 Data: For all specified contents of(R1, R2)

3. Testide genereerimine – mikroprotsessor 1 HLDD-model of a microprocessor: A I IN 10 3 I I R R OUT C 6 Instruction set: A + R 4 7 I1: MVI A,M A  IN I2: MOV R,A R  A I3: MOV M,R OUT  R I4: MOV M,A OUT  A I5: MOV R,M R  IN I6: ADD R A  A + R I7: ORA R A  A  R I8: ANA R A  A  R I9: SUB R RR - 1 I10: MOVC,RCR I11: CMA R,CRC I12: JMPPC, CIFC=0 THEN PC = IN A C A  R 8 A  R 2 I A R A 5 IN 9 R - 1 11 C 12 0 I C PC IN R PC + 1

3. Testide genereerimine – mikroprotsessor 1 3 A I IN Scanning test program: For j=1,n Begin I5: Load R = IN(j1) I1: Load A = IN(j2) I7: ADD A = A + R I4: ReadA End I R C 6 3 A + R I R OUT 7 C 4 A  R A 8 A  R 2 I A R A 5 IN 9 R - 1 11 C 12 0 IN(j2) IN(j1) I C PC IN A R Test data Signature PC + 1

3. Diagnostika üldjuht Rikete maskeerumise näide

x1 x111 x2 x3 3. Diagnostika üldjuht x22 & & 1 1 & 1 1 1 & & & x4 x5 Kahekordne topoloogia rikete maskeeruvuse analüüsiks x6 x610 x7 y x221 1 x8 0 x61 x11 x3 x21 y 0 1 1 x9 1/0 1 1/0 x7 x41 x5 x420 0 & 0/1 x12 x42 0 x8 1 x62 x9 x7 4 SAF (x11 1, x22 1, x42  0, x61  0) are masking each other

x1 x111 x2 x3 3. Diagnostika üldjuht x22 & & 1 & 1 1 1 1 & & & x4 x5 Test gruppide meetod x6 x610 x7 y x221 1 x8 0 x61 x11 x3 x21 y 0 1 1 x9 1 1/0 x420 x7 x41 x5 0 & x12 x42 x8 0 1 x62 x9 x7

CEBE kaks tüüpi sünergiat Meetodite ja algoritmide konversioon Rakendused Arvuti-tehnika Välja-poole suunatud Elektroonika Sisse-poole suunatud Tehnomeedikum

Sünergiaotsingute tulemus Koostöö otsingud CEBE koostöö P1 P2 P5 P7

Protsessorite perekond Koostöö projekti P1 tulemus

P2: Verifitseerimine ja diagnostika Tulemused: Rikete simulaator: • Uus meetod rikete simuleerimiseks, kus on loodud uus matemaatika nii testvektorite kui ka rikete analüüsiks süsteemide diagnostilisel modelleerimisel • Algoritm on suurusjärgu võrra kiirem kui professionaalsed disaini tarkvaratööriistad Doktoritööd: • Maksim Jenihhin. Test Time Minimization for Parellel Hybrid BIST Architectures (2008). Supervisors: R.Ubar, J.Raik. • Sergei Devadze. Fault Simulation of Digital Systems (2009). Supervisors: R.Ubar, P.Ellervee. • Vineeth Govind. DfT-based External Test and Diagnosis of Mesh-like Networks on Chips (2009). Supervisor: J.Raik.

P2: Uued defektide analüüsi meetodid Määramatu (Byzantine’i) rike, X-rikke mudel Simuleerimise aeg 0 1 0 1 Defekt Synopsys X-rikke simulaator Konstantrike Tingimuslik konstant DOT – Hierarhiline testide generaator Võimaldas esmakordselt tõestada defektide liiasust (mitteolulisust) Eri katseskeemid Konstantrikke simulaator, DOT – defektide simulaator

Signaaliprotsessorite arhitektuuride simuleerimine CEBE sünergiast Simuleerimise aeg Professionaalne analoog Miks on ühe objekti puhul simulaator aeglasem? TTÜ simulaator Objektide pere

Protsessorite perekond Testitavuse marker:

CEBE sünergiast Simuleerimise aeg Võimaluse korrelatsiooniomaduse avastamiseks andis koostöö protsessorite pere loomisel Topoloogia omadus Professionaalne analoog TTÜ simulaator Objektide pere

Protsessorite testitavus Deterministic test generation time Random test generation time Fault simulation time Test length Protsessorite perekond

Süsteemide diagnostika Disaini grupp Elektroonika grupp Süsteemi spetsifikatsioon Disainivigade diagnoos Re-Disain Matemaatiline mudel Verifitseerimine Rikete analüüs Testide süntees Koodi katte analüüs Rikete diagnoos Testimine

Tervishoid ruudus - Health2 Tehnoloogia Tehnika-alane teave, disain Meditsiini alane teave Diagnoos, rikete parandamine Testide süntees, verifitseerimine Meditsiini-tehniline seade Doktor Patsient Süsteemi tervis Patsiendi tervis

Evolutionary Health Risk Prevention Tool Synergy: Evolutionary Risk Prevention Tool Health diagnosis tool Sensors, equipments Risk factors Doctors Risks Biosignals Healthcare plan

Health2: Development Objectives System and network design Design and test platform and tools Risk parameter selection Network of sensors, equipments Self repair Data, risk factor values Research Medical knowledge Health diagnosis tool Engineering knowledge Methods, models, and algorithms Risks, risk factors Patients Doctor Medical part Engineering part

CEBE R&D Fields for Health2 System design Signal processing algorithms Research in biomedical engineering Applications Bioimpedance spectrography & tomography Medical equipment Design of dedicated processors Pacemakers Brain research, EEG spectral analysis, SASI marker Design for low power, speed, cost, reliability Mobile SASI analyser Equipments for optical signal measurement Optical dialysis monitoring Design for dependability Optical pulse wave measurement in arteries Verification, design error automated diagnosis and repair Information for doctors Automated testing and fault diagnosis

Bioengineering applications health monitoring systems, body area sensor networks, implantable cardiac pacemakers Laboratories-on-chip impedance spectroscopy in scientific experiments, bio-MEMS products, bioprocessors-on-chip Industrial applications food processing, medical instrumentation, energy conversion Human being Mission critical embedded systems Sensorics, sensor networks Data acquisition bioimpedance, biosignals, biooptical methods Biosignal interpretation Technology micro, nano, MEMS Semiconductor research Defect analysis Test research, fault diagnosis, dependability Dedicated processor architectures, SOC, NOC Bioengineering research brain processes, atherosclerosis, predicting sudden cardiac death, monitoring clinical treatments Signal processing theory, methods, algorithms, non-classical DASP techniques Digital design verification, simulation Analog, mixed signal design Applications: CAD tools Cooperation in CEBE BME RES EMBEL

Health DiagnosisTool Medical knowledge development subtasks Sensor network Biofactors Genetic factors Life style factors Other factors Risk factors (parameters) F11 ... F1m F21 ... F2m Fh1 ... Fhm R1 R2 Rn Health Diagosis Tool Rj = Dj (F11,..., Fhm) Ri Rj Rk Risks Diagnosed risk pattern

RM4Health2: Tasks and Subtasks Theory, models, algorithms, methods, tools > Novelty Engineering development subtasks Tools and platform development subtasks Medical knowledge development subtasks P1 – Blood pressure (Kalju, Mart) P2 – Nefrology (Ivo) P3 – Neurology (SASI – Hiie) P4 – Bioimpedance (Mart) T1 – HL Synthesis (Peeter) T2 – Design (ZamiaCAD/Maksim) T3 – Verification (Jaan) T4 – Debug (Jaan) T5 – Test gener (DECIDER/Jaan) T6 – Fault simulation (Raimund) T7 – Fault diagnosis (Raimund) T8 – BIST/BISD (Raimund) T9 – Test instruments (Artur) Risk factors (Parameters) P1 P2 P3 P4 ... R1 R2 R3 Health Diagosis Tool Risks Diagnosed risk

Health DiagnosisTool Medical knowledge development subtasks Sensor network Biofactors Genetic factors Life style factors Other factors Risk factors (parameters) F11 ... F1m F21 ... F2m Fh1 ... Fhm R1 R2 Rn Health Diagosis Tool Rj = Dj (F11,..., Fhm) Ri Rj Rk Risks Diagnosed risk pattern

On-line testing Cloud At-speed on-line testvectors Fault simulator Fault coverage Off-line Watch-Dog RAM Monitoring checkpoints MUX --- DUT1 DUT2 MUX DUTn Go/NoGo Self-testing system Microprocessor computes off-line the signatures and compares with the real one Signature analyzer VHDL Design with watchdog Functional model for signature calculation Structural model for fault simulation SA MP DUT1 DUT1 DUT1 DUTn DUTn Watch-Dog is connected to different parts of the system for (1) on-line testing, (2) off-line test results analysis (3) test quality evaluation in backgound DUT2 DUT2 DUT2 DUTn

CEBE Seminar Digitaalsüsteemide diagnostika Jäneda mõis, Juuni 17, 2013