Wireless Solution Update

1. Wireless Solution Update Asif Batada Marketing Manager, Wireless Business Unit

2. Agenda • Mobile Base-station Architecture • Basics of Digital IF and Digital Predistortion Linearizer • RF Card Architecture • Predistortion Linearizer Implementation • Conclusion

3. Base-Station Architecture Antenna Mux/De-Mux LVDSw/CDR Digital IF PA A/DD/A Base Band Signal Processing LNA DigitalPredistortion Linearizer HostuP ATMproc Channel Card RF Card Switch Controller Clock Generator Switch I/F Host Processor (CPU) IP Interface RNC RNC I/F Control Board PLD Application

4. Agenda • Mobile Base-station Architecture • Basics of Digital IF and Digital Predistortion Linearizer • RF Card Architecture • Predistortion Linearizer Implementation • Conclusion

5. 1 carrier(5Mhz for UMTS) 120 60 6 Sector Cell 3 SectorCell Digital IF Opportunity • Digital IF is a high volume application for FPGA: • Macro BTS can be configured into two different ways: • 2 carriers for 3 sectors • 1 carrier for 6 sectors • Each BTS has Digital IF Implementation: 6 x EP1S20 Predistortion Implementation: 6 x EP1S10 • 6 x EP1S20 + 6 x EP1S10 per BTS

6. DAC DAC Traditional IF-Based Transmitter • Issues with traditional transmitter • Not flexible to support multiple standards • Non-ideal local frequencies are source of noise • RF and analog components of radio are more difficult to manufacture and have higher reliability issues • Higher cost I BBfilter RFfilter IFfilter + 90º f1 Amp PA Q BBfilter f2

7. DAC Digital IF • With the advancement of data converter technology (100Msps +), it is possible to sample at IF (intermediate frequency) and do Channelization in Digital domain • Advantages of Digital IF • Channel selection can be done in digital domain • Higher precision in frequency selection and shorter settling time of DDS • Good amplitude and phase balance • Extremely linear phase and very low shape factor of base-band filter FIRfilter IFfilter RFfilter  NCO Sym. Mapper FIRfilter Amp PA f2 Digital Up-Converter

8. OutputPower Input Power Add Predistortion Predistortion Linearizer • RF stage (transmitter) uses a linear Power Amplifier (PA) to boost the signals • Linear PAs are very expensive • Some cases it makes up half the cost of BTS • Non-Linear PAs are cheaper • LDMOS based technology • LDMOS introduces distortion of its own • Predistortion in digital domain • Pre-distort the signal so that when it goes thru PA, the overall response is linear • Common technique – Look-up Table based approach • Store the points on the transfer function in a look-up table • One of our customers evaluating 20K400E for this application • Nios is well suited

9. Agenda • Mobile Base-station Architecture • Basics of Digital IF and Digital Predistortion Linearizer • RF Card Architecture • Predistortion Linearizer Implementation • Conclusion

10. RF Card – 1st Generation Design • Customers have either designed their own Digital IF chip (w/o DPD) or are using ASSP (mostly GrayChip) • Limitations with current implementation: • Custom Filter Specs – Adj Channel Power Ratio (ACPR) – Requirement Driven by Architecture • Decimation and Interpolation Ratios – Driven by Standards and Internal implementation • Need to add more carriers • Availability of Multi-Carrier Power Amplifier • Higher capacity channel cards • Higher Data rates over the back plane

11. RF Card I RRC Filter Interpolation ToAnt FromCh. Card (LVDS w/CDR) Input Fmt& Gain Cntrl  NCO DAC Q RRC Filter Interpolation TableAddressCalc(I2 +Q2)1/2 LUT(I & Q) AdaptiveEst. FromPA I & QDemod R S FFT DelayMatching I Compare &Estimate Loop Delay Est RRC Filter Resampler Decimation To Channel Card (LVDS w/CDR) FromAnt NCO  ADC Q RRC Filter Resampler Decimation

12. Agenda • Mobile Base-station Architecture • Basics of Digital IF and Digital Predistortion Linearizer • RF Card Architecture • Predistortion Linearizer Implementation • Conclusion

13. I I - To DUC Q Q Q I TableAddressCalc(I2 +Q2)1/2 LUT(I & Q) ~100 entries12 bit Wordlength Altera MegaCore IP Adaptive Est. R S DelayMatching FFT I & QDemodulator Compare &Estimate Loop DelayEstimator Embedded Processor Altera Solution for DPD

14. x 50 Custom Instruction Example Optional FIFO, Memory, Other Logic Nios Processor Integer Mult / Complex Mult Hardware Accelerator Loop Time = Execution of a single complex multiply Loop Clocks = Number of clocks to execute single iteration MUL Clocks = Number of clocks to execute the MUL only

15. Flow I/P toDPD FromPA DDC UpdateLUT I1 Q1 AddressCalculation . . . . In Qn Sn+1=Sn-*escale Rn+1=Rn-*erotate I1 Q1 FFT Loop DelayMeas . . . . In Qn CmplxMult = tan-1 (.) (.) __ Gain DelayMatching Verror H/W Accelerator ProgrammableLogic Implementation Software Implementation(Nios)

16. Stratix MAC Block Altera MegaCore IP RF Card – Comprehensive Solution I RRC Filter Interpolation ToAnt FromCh. Card (LVDS w/CDR) Input Fmt& Gain Cntrl  NCO Q RRC Filter Interpolation TableAddressCalc(I2 +Q2)1/2 LUT(I & Q) AdaptiveEst. FromPA Arctan I & QDemod R S FFT Stratix Tri-Matrix I DelayMatching Compare &Estimate Loop Delay Est H/W Accelerator RRC Filter Resampler Decimation To Channel Card (LVDS w/CDR) FromAnt NCO  Q RRC Filter Resampler Decimation

17. Advantages of Using FPGA • Greater Flexibility • Filter specification based on ACPR requirements • Optimal filter architecture for most efficient implementation • Support multi-mode capability • Implement Optimal Number of Carriers and Standards • Higher levels of integration • Integration of DPD, Digital IF and Transceivers • Saving board space  Cost savings • Cost Effective Solution • Sub $40 in FPGA; Sub-$20 in HardCopy • Speed and size improvements in FPGA can be easily leveraged to support more channels

18. Conclusion • RF portion of base-station going through revision • Digital Predistortion Linearizer is a key functionality being added • FPGA implementation offer significant advantage over ASSP implementation • Altera Offers comprehensive solution including devices, tools and IP