Reconfigurable DSP Project

1. Reconfigurable DSP Project The Choochoo: MPEG II Decoder Final Design Review JAMM – THE DECODER GROUP School of Electrical and Computer Engineering Georgia Institute of Technology FDR--ECE6276 Class Project 12/06/00

2. Team Members • Sirisha Reddy • Neil Shah • James Tuan • Chris Wood FDR--ECE6276 Class Project 12/06/00

3. Project Requirements • Decoding Instruction Sets for each Profile. • Defining Control Signals and Reservation Tables • Coding and Testing of the decoders for the three profiles. • Support and Integrate with other groups (ISA, Architecture, and DP1) FDR--ECE6276 Class Project 12/06/00

4. Task Distribution • Sequential progress from one profile to the other • Met the deadlines in a timely manner FDR--ECE6276 Class Project 12/06/00

5. Design Considerations • State Machine Approach • MicroCode • Flexibility in translation • Reduces the complexity of controller • Decreases development time • Field updatable FDR--ECE6276 Class Project 12/06/00

6. What we have accomplished • Definitions for the control signals. • IDCT profile. • Inverse Quantization • Motion Compensation • Implementation of the decoder (in VHDL) for all the three profiles. • Testing of the three profiles. FDR--ECE6276 Class Project 12/06/00

7. Support Role • Integration with other groups • Helped DP1 in testing the Profiles. • Architecture • Buses • Multiplexers • Latches • ISA • Minor changes to reduce controller complexity FDR--ECE6276 Class Project 12/06/00

8. Tests and Results • Tested each profile, • Used Program Memory to cycle through each instruction for each profile. • Generated timing diagrams through VHDL • Verified timing diagrams • Successfully tested the instruction sets FDR--ECE6276 Class Project 12/06/00

9. Lessons Learned • Technical Difficulties • ISA • Architecture • DP1 • Communicating with other groups FDR--ECE6276 Class Project 12/06/00