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System Architecture Directions for Networked Sensors

System Architecture Directions for Networked Sensors. Its different !!. Complete systems on a chip Integrated low-power communications Devices that interact with the physical world Microcontrollers with more than just storage and processing capabilities. Network Sensor Characteristics.

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System Architecture Directions for Networked Sensors

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  1. System Architecture Directions for Networked Sensors

  2. Its different !! • Complete systems on a chip • Integrated low-power communications • Devices that interact with the physical world • Microcontrollers with more than just storage and processing capabilities

  3. Network Sensor Characteristics • Small physical size and low power consumptions • Concurrency-intensive operations • Limited Physical Parallelism and Controller Hierarchy • Diversity in Design and Usage • Robust Operation Slide 10

  4. Network Sensor Schematic Diagram

  5. Power Characteristics • Three modes • Active • Idle • Inactive • In the cost of transmitting and receiving a bit the processor can execute 100 instructions

  6. TinyOS • Event based model • High concurrency • Asynchronous communication • Elements of TinyOS • Tiny scheduler • Simple FIFO scheduler • Bounded size scheduling data structure • Power aware • Components • Command Handlers • Event Handlers • Frame • Threads

  7. Components • Describe resources they provide and require • Communication across components take place through a function call – but non-blocking • Classified as • Hardware abstraction • Synthetic hardware • High level software

  8. Components (2) • Commands • Higher level to lower level • Asynchronous request • Provides status information to caller • Signals • Lower level to higher level • Event handlers • Invoked to deal with hardware events • Lower level components have handlers connected to hardware events

  9. Components (3) • Threads • Perform primary work • Atomic and run to completion • Do not block or spin wait

  10. Evaluation • Entire application size – 226 bytes data memory and 3kB instruction memory • Posting thread and context switching – 6 bytes moving time • Propagation delay - 90ms • Supports data rates of 25Kbps • Implemented on source based multi-hop routing, active-badge-like location detection and sensor network monitoring applications. Slide 3

  11. Advantages/Features • Precursor to architectural innovations for network sensor systems • Single microcontroller can support multiple data flows • Provides means to predict impact of architectural changes in microcotrollers • Supports reconfiguration and hence is versatile

  12. Advantages/Features (2) • Rids the programmer from having to write own scheduler/dispatcher • Provides extensive static information to remove overhead and analyze performance

  13. Related Work • Real time embedded OS – PalmOS, WinCE • Real time executives – Creek, pOSEK • Piconet and Active Badge Location Systems

  14. Issues • Does not speak about real-time gaurantees • Run-to-completion semantics – what about priority, pre-emption?? • No mention of Testing / Debugging support • Reliable communication – no buffer • Security mechanism – maincontroller can be reprogrammed over the network

  15. Summary • Event driven operating system • Support for efficient modularity and concurrency intensive operations • 178 bytes of memory • Propogation delay 1.25 bytes memory time • Context switch 6 bytes memory time • Groundwork for architectural advances

  16. Questions ???

  17. Thank You Vishal Kudchadkar vkudchad@usc.edu

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