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Progress report

Progress report. Yung- Chih Chen. Done. Current detector. Synthesis for BDD-based SET arrays. a. f = a’b’+ab. 00 11. b. b. 1. 0. 1. Boolean function. BDD. Product term. SET array. Ongoing. Threshold logic gate implementation by using a BDD-based SET array. a b c d. 3.

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Progress report

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  1. Progress report Yung-Chih Chen

  2. Done Current detector • Synthesis for BDD-based SETarrays a f = a’b’+ab 00 11 b b 1 0 1 Boolean function BDD Product term SET array

  3. Ongoing • Threshold logic gate implementation by using a BDD-based SET array a b c d 3 2 1 1 1 f High Low a b c d Short Open

  4. Threshold logic network T w w w w T w w w w T w w w w T w w w w

  5. SETarray partition Conventional logic network Threshold logic network

  6. Done • Node merging • Node addition and removal A A B B A A B B C

  7. Application • Bounded Sequential Equivalence Checking (BSEC) • unroll circuits → construct a miter → SAT PI PI PI PI F F F F S0 . . . G G G G PO PO PO PO . . . T=0 T=1 1 T=n-1 T=n

  8. F F F F . . . G G G G Ongoing • Speed up SAT-based sequential equivalence checking

  9. Current flow Miter Unrolling F F0 Fn NM/NAR . . . G G0 Gn PO PO PO

  10. Experimental results

  11. Experimental results

  12. Experimental results -NAR

  13. Experimental results - NTHUCAD

  14. Project • Automated mapping for SET arrays • Single output • Multiple outputs • Partition • Threshold logic • Rewiring • Equivalence checking • Threshold logic implementation by using SET arrays

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