Experience with the MVD

1. Experience with the MVD Living around the beam pipe Components, connections, signals, systems Hubert van Hecke - Los Alamos

2. pads Si strips MCM 1/2 MVD without cover Power/comm board End plates

3. Living around the beam pipe • Every year we had to clear the beam pipe The central magnet is moved every year The beam pipe was not where it was supposed to be The beam pipe is supported in the CM iron/nosecone Beam pipe Official supports Non-official supports Nosecone MVD support plate Understand environment

4. Provide for easy movement of the NCC halves or Ensure that the NCC clears the beam pipe for all positions of the CM Flanges, supports, bigger diameter or Have the supports mounted to the NCC itself

5. connections and signal paths

6. silicon strips and pads Silicon strips 5x8 and 5x5 cm 256 strips 200 um pitch Silicon pads 252 pads (12 cols, 21 rows) 2x2 - 6x6 mm double metal traces lay over pads simplify connections Incur few % crosstalk

7. silicon to kapton cable Dry adhesive was used to bond Silicon to Kapton Wire bonds were encapsulated in black potting material (clear potting cured but stayed more sticky) cannot inspect bonds visually

8. kapton cables Kapton cables 6, 8, 14, 19 cm long 0.05mm Kapton Traces: 0.005mm Cu (x .5 area) Ground: 0.005mm Cu (x .1 area) The extreme thinness and the (almost) absence of shielding ground planes was driven by the requirement to keep the mass facing the central arms low.

9. noise pickup in thin cables Si MCM Fatal noise levels in the strip detectors Do system tests early

10. MCM MCM 19 chips: 8 32-channel preamp / discriminators, 8 32-channel AMU / ADC, 2 Xilinx, 1 opamp in a 5x5cm package. Produces a digital data packet. • Low yield, but the ones that worked never failed • Discriminator never worked • Xilinx programming proved a vulnerability Need more time for ASIC development have Xilinx programmer in-house

11. output cable Output cable 50 traces, 0.5mm pitch, controlled thickness and width Analog, digital, reference voltages, 10, 40 MHz clocks, serial controls, data out.

12. MCM to power/comm board Vertical spacing to << 0.5mm Limited space, so made custom tools for opening/closing ZIF connectors ZIF connectors, Elco 0.5mm pitch. Rated for 50 open/close, good for much more 160-pin JAE Power/comm board

13. power/comm to motherboard Board spacing 9mm Fixture to hold and push up to 6 160-pin connectors Trace density in vicinity of the 160-pin connectors forced the motherboard to be 14-layer

14. motherboard to cables The diameter of the MVD enclosure (60 cm) was determined by the area taken up by the cable connectors, not by the actual Si detectors. Keeping moist air out is necessary if you run the detector below the dew point. Some connectors were very leaky, and required insulating foam barriers. Signal cables were .05” pitch solid-core ribbons, vulnerable to bending failure. Strain relief clips were iron and not used because of the mag. field Cables are flexible, bundles are not (recall the yearly uninstall / reinstall) Connectors were on a surface that was not accessible after installation. Need ALL components designed before starting mechanical design

15. downstream electronics • AIM - Arcnet Interface module: arcnet fiber to copper • TCIM - Timing and Control Interface Module: mode bits fiber to copper • DCIM - Data Collection Interface Module: data demultiplexing, multiplexing module, copper to fiber Downstream electronics was badly designed and unsupported by the designers. Needed more development time Need system tests, not just single boards Need designers to remain on the team (long enough) Xilinx programmers on the team

16. conclusions (Other than the ones I’ve already marked) Need to do complete system tests early Need electronics systems engineer on the project Need designers to remain on the project Need more lead time for many components