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Introduction

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Introduction

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  1. 3D ASICs program at Fermilab Fermilab ASIC Design Group (G.Deptuch, F.Fahim, J.Hoff, M.Trimpl, A.Shenai, T.Zimmerman)R.Yarema – retiredD.Christian, R.Lipton, T.Liuand collaboratorsfrom:BNLUptonNY, SLACMenlo Park CA, AGH-USTKraków PolandUS Universities: Brown U., Cornell U.and industrial partners:TezzaronNaperville IL, ZiptronixMorrisville NC, RTI Research Triangle Park NC, ALLVIA Sunnyvale CA, CVInc. Dallas TX,

  2. Introduction Environment of integrated circuits technology for radiation detector readout systems is: • Competitive • Investments hungry • Characterized by long gaining experience curves for the ASIC groups • Challenging due to restrictions in access to the cutting edge technologies, legalities and bureaucratic burden associated with it Groups tend to emphasize on one or a few particular detector technologies, families of design blocs, design methodologies or assembly works and excel offering complementary sets of skills and tools to the community Fermilab advanced 3D-IC technology gaining the World leading position AEM Nov. 4, 2013

  3. Motivation 3D chip is composed of two or more layers of active electronic components and featureshorizontal intra-tierand vertical inter-tier connectivity, Distinguishingfeatures of 3D technologies: 4Through Silicon Vias (TSV)5Bonding5Wafer thinning5Back-side processing3 Transformational change: 4Finer pitch pixels 5Less mass 5Higher localized “on detector” functionality 5Bump bond alternative 5Non dead space arrays 3 Long-term goal: Support: glassor Si interposer 3D ASIC with TSVsthreadingconnections Large-areaseam-less sensor Strategic goal: 4 side buttable, dead-area-free detectors for uses rangingfromX-ray, visible, IR imaging to classical tracking 3 AEM Nov. 4, 2013

  4. Review: design VIP2b VIP2b 3D design for the ILC pixel VXT: 4 AEM Nov. 4, 2013

  5. Review: design VICTR VIP2b 3D design for the ILC pixel VXT: 5 AEM Nov. 4, 2013

  6. Review: design VIPIC1 6 AEM Nov. 4, 2013

  7. Design of VIPIC1 - 1 VIPIC1(Prototype) is designed to quickly count the number of hits inevery pixel and read out the # of hits, and addresses in a deadtimeless manner, Active area: 5120×5120 μm2, chip: 6.3×5.5 mm2 Matrix of 64×64 pixelsdividedinto 16 group of 4×64 pixelsreadthrough one LVDS buffer Sparsificationengineselects hit pixels in everygroup for readout Onlydigitalinformationread out (160 ns /hit pixel) moredetails: G.Deptuch, M.Demarteau, J.Hoff, R.Lipton, A.Shenai, M.Trimpl, et al., “Vertically Integrated Circuits at Fermilab“,IEEE Transaction on Nuclear Science, vol. 57, no. 4, (2010), pp. 2178-2186 G.Deptuch, M.Trimpl, R.Yarema, D.P.Siddons, G.Carini, R.Szczygieł, P.Grybos, P.Maj, “VIPIC IC - Design and Test Aspects of the 3D Pixel Chip”, Proceedings of Nuclear Science Symposium, Knoxville, USA, October2010 G.Deptuch, G.Carini, P.Gryboś, P.Kmon, P.Maj, M.Trimpl, D.P.Siddons, R.Szczygieł, R.Yarema, „Design and Tests of the Vertically Integrated Photon Imaging Chip” – submitted to IEEE Transaction on Nuclear Science 7 AEM Nov. 4, 2013

  8. Design of VIPIC1 - 2 Analog:280 transistors Digital:1400 transistors 12-bit for configuration7-bit trim offset, 3-bit trimRf,single/difmode, CAL enable 4in-pixel 1-stage pipe-line logic 4disributedsparsifier: 8 bit priority encoder, pixel readout selector, pixeladdress generator and counteroutput 42×5-bit longcounters4configurationregisters:single bit / pixel(pixel SET, pixel RESET) and 12 bit DAC and configuration (calib., singl./diff.) 4Single endedor pseudo-differential CSA-shaping filter-discriminator: shaping time tp=250 ns, power ~25 mW / analog pixel, noise <150 e- ENC, gain(Cfeed=8fF) = ~115mV/8keV (optimized for 8 keV in Si - linearityupto 3×8 keV) 41 thresholddiscriminator 410bit/pixel DAC adjustments 2-lines for CAL circuits discriminatoroutput Doubledbondpads for eachsignal Power supliestied between tiers 8 AEM Nov. 4, 2013 Pixel 80x80 mm2

  9. Fabrication of VIPIC1 - 1 Via middle – TSV in foundryafter FEOL 130nm CMOS 6M1P 1st 3D-IC MPW RUN • 3D-IC Consortium established in late 2008, 17 members; 6 countries+Tezzaron • Fermilabset up 1st 3D-IC MPW for HEP-MPW frame accepted for fab in 03/2010 • 1st working chips gotfrom 2 bondedpairs of wafers (TC) in 06/2012 • March-May-June 2013 last 3D bondedwafers (TC and DBI) yieldingmoregood chips Face-Face TS Vias (f=1mm) Ziptronix / licensed to Novati Tezzaron / Novati Betteryields observed 9 AEM Nov. 4, 2013

  10. Tests VIPIC1 electrical - 1 80 mm pitch 100 mm pitch Map of pixels with noise (scale: black – 0 mV rms, white – 10 mV rms) skippedrow skippedcolumn Layoutof ”to sensor pads” on VIPIC1 original80 mm - pitchpadsfor BNL sensorsoverlaid with 100 mm pitchpads for Hamamatsu sensors 4 Hamamatsu baby sensorsavailable as singulateddies, decided to be usedwhilewaiting for ultimatebonding of BNL sensorsusing the DBI process Noise (ENC) calculatedusinggain from calibration with chargeinjection 10 AEM Nov. 4, 2013

  11. Tests VIPIC1 bumpbonded to sensor - 1 500 mm thick back-side of sensor Wirebondingpads 4 100 mm pitch Hamamatsu pixel baby-sensor with Sn-Pb bumps 4 depositiontechnique on a single die with ENIG UBM on Al substratepads by (CVInc.) – padsf=60 mm 4UBM deposited on VIPIC (ENIG padsarebondable) 4 300 mm thick Hamamatsu pixelsensor mounted on top of VIPIC (75mm bump,post reflow gap at 45mm to 50mm prior to addition of underfill) 4 Optimization of the Ni-Au depositionled to almost 100% of padsretaining UBM and bumps 11 AEM Nov. 4, 2013

  12. Tests VIPIC1 bumpbonded to sensor - 2 Transmission radiogram of a small W mask (2.5×2.5 mm2) placed atop of the sensor back-side illuminated and fully depleted ROIC area mask has features smaller than the sensor pitch, e.g. center hole f=75 mm 2G W mask with Fermilab logo observations rows & colsskipped 4 55Fe sourceused 4 Allsignals integrated above threshold set higherthannoise 4Onlyverylimitednumber of pixelsareinsensitive 4significantgaindispersions 2 Detector biased at 120V (fulldepletion)109Cd and 55Fe used 4 Fullsparsifiedreadout(fromall16groupsof4×64pixels) used 4Acquisition run for a fewhours to accumulateenough of statistics 12 AEM Nov. 4, 2013

  13. Tests VIPIC1 bumpbonded to sensor - 3 Selected results from a single pixel from a run with flat field illumination 4 Scanning of thresholds (vt2-vt1) with fine 0.5mV/step resolution 4 Full sparsified readout using 50MHz data serialization clock simultaneouslyfrom every group 4 Duration of a single readout cycle ~80ms (timing precision) 4 Reference data without source 4Sourcesused:- 109Cd 22keV (1mCi)- 55Fe 5.9keV (10mCi) 4 5.9 keVphoton à1640 e-/h+ Gain=(420-350)mV/ph*1ph/1640=43mV/e- Noise=3.5mVrms*1e-/43mV = 83e-rms Response gets stronglynonlinearaboveapproximately18keV Detector biased at 120V (fulldepletion) 109Cd 22keV and 55Fe 5.9keV Definite analyses (noise, gain, statistics) are underway… as well as devices bonded to 64 ×64 pixelsensorsareexpectedbefore the end of 2013 13 AEM Nov. 4, 2013

  14. Invitation AEM Nov. 4, 2013

  15. Invitation AEM Nov. 4, 2013

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