輔仁大學電子工程學系 呂學坤 教授

1. Yield- and Reliability-Enhancement Techniques for Random Access Memories 輔仁大學電子工程學系 呂學坤 教授

2. Outline • Introduction • Test Challenges • Traditional Test Strategies vs. SOC Testing • Essential Spare Pivoting (ESP) • Typical BISR Architectures • DWL and DBL Structures • Redundancy Allocation Problem for DWL and DBL Architectures • The Problem • Graph Model and Complexity Analysis • Built-In Redundancy Analysis • Repair Rate and Hardware Overhead Analysis • Conclusions

3. Introduction

4. Component provider Design and test development Design and test development Manufacturing Test System integrator Design and test development Design and test development Manufacturing Manufacturing Test Test SOC Test Specifics

5. SOC Test Challenges • Core-Internal Tests • The development of high-quality, but relatively inexpensive tests for cores. • Traditional fault models and related ATPG tools are increasingly inadequately. • Core Test Knowledge Transfer • Core-internal DFT, test modes and test protocols, fault coverage, test pattern data, etc. • Test Access to Embedded Cores • System Chip Test Integration and Optimization • The system-chip integrator is confronted with many optimization issues.

6. Importance of Memory Testing • Memory testing is a more and more important issue • RAMs are key components for electronic systems • Memories represent about 30% of the semiconductor market • Embedded memories are dominating the chip yield • Memory testing is more and more difficult • Growing density, capacity, and speed • Emerging new architectures and technologies • Embedded memories: access, diagnostics & repair, heterogeneity, custom design, power & noise, scheduling, compression, etc. • Cost drives the need for more efficient test methodologies • IFA, fault modeling and simulation, test algorithm development and evaluation, diagnostics, DFT, BIST, BIRA, BISR, etc. • Test automation is required • Failure analysis, fault simulation, ATPG, and diagnostics • BIST/BIRA/BISR generation

7. Redundancy and Repair • Problem: • We keep shrinking RAM cell size and increasing RAM density and capacity. How do we maintain the yield? • Solutions: • Fabrication • Material, process, equipment, etc. • Design • Device, circuit, etc. • Redundancy and repair • On-line • EDAC (extended Hamming code; product code) • Off-line • Spare rows, columns, blocks, etc.

8. Redundancy Architectures

9. Reconfiguration Mechanism Redundancy Analyzer RAM MUX Spare Elements BIST RAM Built-In Self-Repair (BISR) • BIST BISD  BIRA  BISR

10. From BIST to BISR BIST BISD BIRA BISR • BIST: built-in self-test • BIECA: built-in error catch & analysis • BISD: built-in self diagnosis • BIRA: built-in redundancy analysis • BISR: built-in self-repair

11. Example Block with Faulty Cells

12. Repair-Most (RM) • Run BIST and construct bitmap • Construct row and column error counters • Run Must-Repair algorithm • Run greedy final-repair algorithm

13. Essential Spare Pivoting (ESP) • Maintain high repair rate without using a bitmap • Small area overhead • Fault Collection (FC) • Collect and store faulty-cell address using row-pivot and column-pivot registers • If there is a match for row (col) pivot, the pivot is an essential pivot • If there is no match, store the row/col addresses in the pivot registers • If F > r+c, the RAM is irreparable • Spare Allocation (SA) • Use row and column pivots for spare allocation • Spare rows (cols) for essential row (col) pivots • SA for orthogonal faults Ref: Huang et al., IEEE TR, 11/03

14. ESP Example (1,0) (1,6) (2,4) (3,4) (5,1) (5,2) (7,3)

15. Repair Rate (r=10)

16. Redundancy Organization SEG0 SEG1 SR0 SCG0 SCG1 SR1 SR: Spare Row; SCG: Spare Column Group; SEG: Segment ITC03

17. BISR Architecture Q D A Main Memory Wrapper MAO BIRA POR BIST Spare Memory MAO: mask address output; POR: power-on reset

18. Power-On BISR Procedure

19. Basic BIST Module

20. BIRA Module

21. Block Diagram of ARU

22. An Industrial Case

23. A 8Kx64 Repairable SRAM Technology: 0.25um SRAM area: 6.5 mm2 BISR area : 0.3 mm2 Spare area : 0.3 mm2 HOspare: 4.6% HObisr: 4.6% Repair rate: 100% (if # random faults is no more than 10) Redundancy: 4 spare rows and 2 spare column groups Group size: 4

24. Memory Defect Injection Fault Translation Faulty Memory Spare Elements RA Algorithm Test Algorithm Simulation RA Simulation Result Fail bit map and sub-maps Ref: MTDT02 RA Algorithm Evaluation by Simulation

25. Switching Gate Divided Word-Line (DWL) Structure • The main advantage of DWL structure is that the power down technique for unused circuit can save power consumption significantly. Row Bank Select Line Word-Line ... Sub Word-Line Memory ... ... ... Cell Row Bank Row Block

26. Divided Bit-Line (DBL) Structure Memory cell Bit-Line Switching transistor Word-Line . . . Column Bank Select Line Sub Bit-Line Column Block

27. Hybrid Architecture

28. Column bank 0 Column bank 1 Redundancy Analysis (Cont.)

29. Redundancy Analysis (Cont.) Spare column block Spare row block

30. Redundancy Analysis (Cont.) Row bank 0 Row bank 1

31. Divided array 00 DA00 Redundancy Analysis (Cont.)

32. Switching Gate Global Word Line Row Block Column Bank Select Line (CBS) Switching Transistor Global Bit Line Local Bit Line Column Block Local Word Line Row Bank Select Line Divided Array

33. Problem Modeling and Complexity Analysis • The conjunctive form (CF) of the allocation problem for the following figure can be formalized as follows [2]: CF = (R0 + C0)(R0 + C1) (R0 + C2) (R0 + C3) (R0 + C4) (R2 + C3)(R4 + C3)(R4 + C7)(R5 + C7)(R6 + C7) where - Ri denots row i, - Cj denotes column j, [2] Kuo and Fuch “Efficient spare allocation in reconfigurable arrays,” IEEE Design & Test of Computer, vol. 4, pp. 24-31, 1987

34. Problem Modeling and Complexity Analysis • Transform the problem in polynomial time to the bi-partite graph clique problem. • The complexity of the repair problem is NP-complete Graph Modeling

35. Problem Modeling and Complexity Analysis • The conjunctive form of the allocation problem for the following faulty bitmap can be formalized as follows: CF = (R00+C00) (R00+C10) (R00+C20) (R00+C30) (R20+C30) (R40+C31) (R01+C40) (R41+C71) (R51+C71) (R61+C71), where - Rij: global row address i and row bank index j, - Ckl : global column address k and column bank index l, - Rijand Ckl are both Boolean variables.

36. Graph Modeling Problem Modeling and Complexity Analysis

37. Problem Modeling and Complexity Analysis • Is this an NP-complete problem? • The formal approach to prove if the complexity of a problem is NP-complete contains the following two steps : (a) show that the problem is in the class of NP problem. (b) find a problem in the NP class that can be transformed to our problem in polynomial time.

38. Problem Modeling and Complexity Analysis

39. Problem Modeling and Complexity Analysis

40. Extended Local Repair-Most Approach (ELRM) • Two procedures: • Bitmap construction ~ BCFLRM( ) • Block allocation ~ BAFLRM( ) • The local bitmap for each column bank is constructed by using BCFLRM ( ). Redundancy row/column blocks are allocated by using BAFLRM ( ). • The addresses of faulty cells will be stored temporarily and compared with the contents of address register in procedure BCFLRM ( ). • A new tag will be used if the address of the currently detected faulty cell is different from that of any previously stored addresses in the bitmap.

41. Local Bitmap (LMB) p q

42. An Example

43. An Example

44. An Example 3 1

45. An Example 3 1

46. An Example

47. An Example

48. An Example 3 1

49. An Example 3 1

50. An Example