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Beam Secondary Shower Acquisition System: Igloo2 GBT Implementation Upgrade

Beam Secondary Shower Acquisition System: Igloo2 GBT Implementation Upgrade. Student Meeting Jose Luis Sirvent PhD. Student 07/04/2014. GBT-FPGA Overview in Igloo2 (Clock Management). GBT_BANK (Very simplified view). SERDES_INIT_MASTER APB_BUS (PLL). Data_In (83 bits) @40Mhz.

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Beam Secondary Shower Acquisition System: Igloo2 GBT Implementation Upgrade

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  1. Beam Secondary Shower Acquisition System:Igloo2 GBT Implementation Upgrade Student Meeting Jose Luis Sirvent PhD. Student 07/04/2014

  2. GBT-FPGA Overview in Igloo2(Clock Management) GBT_BANK (Very simplified view) SERDES_INIT_MASTER APB_BUS (PLL) Data_In (83 bits) @40Mhz Tx_Word (19 bits) @ 240MHz Tx_CLK (240MHz) GBT_TX Scrambler Encoder Gearbox GBT_MGT SERDES_0 Vendor Specific IP TX_Data_P (4.8Gbps) TX_Data_N (4.8Gbps) TX_Word_CLK (240MHz) TX_Frame_CLK (40MHz) RefCLK1_P (120MHz) RefCLK1_N (120MHz) Rx_CLK (240MHz) RX_Data_P (4.8Gbps) RX_Data_N (4.8Gbps) Rx_Word (19 bits) @ 240 MHz Data_Out (83 bits) @ 40Mhz GBT_RX Gearbox Decoder Descrambler RX_Word_CLK (240MHz) RX_Frame_CLK (40MHz) RX_PLL TX_PLL

  3. GBT-FPGA on Igloo2:The MGT block

  4. GBT-FPGA on Igloo2: Testing GBT_TX & GBT_RX modified modules • It was needed to verify that the TX & RX modules work well with the modifications done. • Dual Port Rams Xilinx IPs substituted by MicrosemiIps (GBT-FPGA STD Version) • Design unconstrained up to now. (Improvements are spected) 84 Bits @ 40MHz 20 Bits @ 240MHz 84 Bits @ 40MHz GBT Frame: Data visible to GBT-TX and from GBT-RX 84 bits @ 40MHz

  5. GBT-FPGA on Igloo2 : Testing GBT_TX & GBT_RX modified modules • It was needed to verify that the TX & RX modules work well with the modifications done. • Dual Port Rams Xilinx IPs substituted by MicrosemiIps (GBT-FPGA STD Version) • Design unconstrained up to now. (Improvements are spected) 84 Bits @ 40MHz 20 Bits @ 240MHz 84 Bits @ 40MHz

  6. GBT-FPGA on Igloo2 : Testing GBT_TX & GBT_RX modified modules • TX & RX Frame CLK: Comes from the same FRAME_CLK (40MHz) • TX & RX Word CLK: Comes from the same WORD_CLK (240 MHz) • Both clocks are artificially injected in the TestBench. • The TX & RX frames are well recovered with a delay ~ 320ns.

  7. GBT-FPGA on Igloo2 : Let’s connect all together  GBT_TX, GBT_MGT & GBT_RX 84 Bits @ 40MHz 20 Bits @ 240MHz 84 Bits @ 40MHz 1 Bit @ 4.8GHz 20 Bits @ 240MHz Simulation with static Frame: 0x0000BABEAC1DADCDCFFFF Static frame well recovered!!

  8. GBT-FPGA on Igloo2 : Let’s connect all together  GBT_TX, GBT_MGT & GBT_RX 84 Bits @ 40MHz 20 Bits @ 240MHz 84 Bits @ 40MHz 1 Bit @ 4.8GHz 20 Bits @ 240MHz Simulation with dynamic Frame: Segmented counter Delay ~ 314 ns (Non deterministic, STD Version) Dynamic frame well detected!! We see the TX & RX Flags for delay determination

  9. GBT-FPGA on Igloo2 : Comparing data with specked results from LATOP version 130.3 ns Slide from Manoel Barros Marin

  10. GBT-FPGA on Igloo2 : Next Steps…. we are almost done with this • Verify practically the simulation results  Program the FPGA and see • Start applying optimizations in the code  Solve some warnings and apply constrains • Study possible synchronization issues  Check that these results are not a mirage • Check initialization sequence  It’s very important for the correct operation • Check the repetitively of the link latency  maybe there are very few changes… • Include UART modules for USB Communication  Better resources for debugging • Start with TWEPP’14 Abstract: • Deadline 30/04/2014 and need approval from Bernd & Rhori Jones

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